XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 55

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

Configuration Sequence
There are four major steps in the XC4000-Series power-up
configuration sequence.
• Configuration Memory Clear
• Initialization
• Configuration
• Start-Up
The full process is illustrated in
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested.
asserted, the logic initiates one additional clearing of the
configuration frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay of 50 to 250 s (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac-
tive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
September 18, 1996 (Version 1.04)
Figure
48.
If neither is
Figure 48: Power-up Configuration Sequence
SAMPLE PRELOAD
(* if PROGRAM = High)
SAMPLE/PRELOAD
SAMPLE/PRELOAD
Boundary Scan
CONFIGURE
CONFIGURE*
READBACK
Instructions
Available:
EXTEST*
BYPASS
BYPASS
BYPASS
EXTEST
USER 1
USER 2
Master CCLK
Goes Active
If Boundary Scan
is Selected
F
Configuration Memory
Configuration Memory
One Time-Out Pulse
Test M0 Generate
Completely Clear
Data to DOUT
of 16 or 64 ms
Keep Clearing
Configuration
Configuration
Count Equals
Data Frame
Mode Lines
Operational
Once More
Yes
Yes
Yes
Sequence
Load One
No
Start-Up
memory
High? if
Sample
Master
Config-
uration
Length
>3.5 V
Frame
CCLK
Count
Error
Pass
V
INIT
Full
CC
Yes
Yes
No
No
No
No
Master Waits 50 to 250 s
Before Sampling Mode Lines
~1.3 s per Frame
Pull INIT Low
and Stop
PROGRAM
= Low
Yes
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