AT94K40AL-25BQC Atmel, AT94K40AL-25BQC Datasheet - Page 146

• Manufacturer Part Number: AT94K40AL-25BQC
• Description: IC FPSLIC 40K GATE 25MHZ 144LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K40AL-25BQC

• Core Type: 8-bit AVR
• Speed: 18MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.30.1.2
4.30.1.3
146
AT94KAL Series FPSLIC
Master Receiver Mode
Slave Receiver Mode
cleared by software before the 2-wire Serial Transfer can continue. The TWINT flag is cleared by
writing a logic 1 to the flag.
When the Slave address and the direction bit have been transmitted and an acknowledgment bit
has been received, TWINT is set again and a number of status codes in TWSR are possible.
Status codes $18, $20, or $38 apply to Master mode, and status codes $68, $78, or $B0 apply to
Slave mode. The appropriate action to be taken for each of these status codes is detailed in
Table
carded, and the Write Collision bit, TWWC, will be set in the TWCR register. This scheme is
repeated until a STOP condition is transmitted by writing a logic 1 to the TWSTO bit in the
TWCR register.
After a repeated START condition (state $10) the 2-wire Serial Interface may switch to the Mas-
ter Receiver mode by loading TWDR with SLA+R.
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter,
see
condition has been transmitted, the TWINT flag is set by the hardware. The software must then
load TWDR with the 7-bit Slave address and the data direction bit (SLA+R). The 2-wire Serial
Interrupt flag must then be cleared by software before the 2-wire Serial Transfer can continue.
When the Slave address and the direction bit have been transmitted and an acknowledgment bit
has been received, TWINT is set again and a number of status codes in TWSR are possible.
Status codes $40, $48, or $38 apply to Master mode, and status codes $68, $78, or $B0 apply to
Slave mode. The appropriate action to be taken for each of these status codes is detailed in
Table
by the hardware. This scheme is repeated until a STOP condition is transmitted by writing a logic
1 to the TWSTO bit in the TWCR register.
After a repeated START condition (state $10), the 2-wire Serial Interface may switch to the Mas-
ter Transmitter mode by loading TWDR with SLA+W.
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter,
see
follows:
Table 4-27.
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the 2-wire Serial Interface will respond to the general
call address ($00), otherwise it will ignore the general call address.
Table 4-28.
TWAR
value
TWCR
value
Figure
Figure
4-30. Received data can be read from the TWDR register when the TWINT flag is set High
4-29. The data must be loaded when TWINT is High only. If not, the access will be dis-
4-49. The transfer is initialized as in the Master Transmitter mode. When the START
4-50. To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as
TWAR: Slave Receiver Mode Initialization
TWCR: Slave Receiver Mode Initialization
TWA6
Device’s own Slave address
TWINT
0
TWA5
TWEA
1
TWA4
TWSTA
0
TWA3
TWSTO
0
TWA2
TWWC
0
TWA1
TWEN
1
TWA0
-
0
1138I–FPSLI–1/08
TWGCE
TWIE
X