AT94K40AL-25BQC Atmel, AT94K40AL-25BQC Datasheet - Page 88

• Manufacturer Part Number: AT94K40AL-25BQC
• Description: IC FPSLIC 40K GATE 25MHZ 144LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K40AL-25BQC

• Core Type: 8-bit AVR
• Speed: 18MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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AT94KAL Series FPSLIC
Boundary-scan Description Language Files
Table 4-12.
Boundary-Scan Description Language (BSDL) files describe Boundary-Scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-Scan data register are included in this description. A BSDL file for AT94K Family
is available.
Enable Clock - TOSC 1
Enable Output - SDA
Enable Output - SCL
Clock Out/In - SCL
Data Out/In - SDA
Bit EXTEST and SAMPLE_PRELOAD (Continued)
AVR Reset
Bit Type
EXTEST
1 = clock disabled. Capture-DR
grabs clock enable from the AVR.
Observe only. Capture-DR grabs
signal from pad.
1 = drive “0”
0 = drive disabled, bus pull-up
Capture-DR grabs output enable
scan latch.
Observe only. Capture-DR grabs
signal from pad.
1 = drive “0”
0 = drive disabled, bus pull-up
Capture-DR grabs output enable
scan latch.
Internal, observe only.
Capture-DR grabs internal AVR
reset signal.
SAMPLE_PRELOAD
Capture-DR grabs enable from
the AVR.
Capture-DR grabs signal from
pad.
Capture-DR grabs output enable
from the AVR.
Capture-DR grabs signal from
pad.
Capture-DR grabs output enable
from the AVR.
Capture-DR grabs internal AVR
reset signal.
1138I–FPSLI–1/08