AT94K40AL-25BQC Atmel, AT94K40AL-25BQC Datasheet - Page 71

• Manufacturer Part Number: AT94K40AL-25BQC
• Description: IC FPSLIC 40K GATE 25MHZ 144LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K40AL-25BQC

• Core Type: 8-bit AVR
• Speed: 18MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.18
4.18.1
4.18.2
4.18.3
1138I–FPSLI–1/08
JTAG Interface and On-chip Debug System
Features
Overview
The Test Access Port – TAP
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The AVR IEEE std. 1149.1 compliant JTAG interface is used for on-chip debugging.
The On-Chip Debug support is considered being private JTAG instructions, and distributed
within ATMEL and to selected third-party vendors only.
Figure 4-16
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(shift register) between the TDI - input and TDO - output. The Instruction Register holds JTAG
instructions controlling the behavior of a Data Register.
Of the Data Registers, the ID-Register, Bypass Register, and the AVR I/O Boundary-Scan Chain
are used for board-level testing. The Internal Scan Chain and Break-Point Scan Chain are used
for On-Chip debugging only.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port - TAP. These pins are:
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not
provided.
• TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state
• TCK: Test Clock. JTAG operation is synchronous to TCK
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction register or Data Register
JTAG (IEEE std. 1149.1 Compliant) Interface
AVR I/O Boundary-scan Capabilities According to the JTAG Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
On-chip Debugging Supported by AVR Studio version 4 or above
machine.
(Scan Chains)
– All Internal Peripheral Units
– AVR Program and Data SRAM
– The Internal Register File
– Program Counter/Instruction
– FPGA/AVR Interface
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Breakpoints on Single Address or Address Range
– Data Memory Breakpoints on Single Address or Address Range
– FPGA Hardware Break
– Frame Memory Breakpoint on Single Address
shows a block diagram of the JTAG interface and the On-Chip Debug system. The
AT94KAL Series FPSLIC
71