ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet
ADSP-3PARCBF548M01
Specifications of ADSP-3PARCBF548M01
Related parts for ADSP-3PARCBF548M01
ADSP-3PARCBF548M01 Summary of contents
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... INSTR SRAM DATA SRAM EAB 64 DEB 32 EXTERNAL PORT NOR, DDR, MDDR DDR/MDDR ASYNC 16 16 Figure 1. ADSP-BF549 Functional Block Diagram One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Embedded Processor WATCHDOG OTP TIMER HOST DMA INTERRUPTS UART (0-1) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TABLE OF CONTENTS General Description ................................................. 3 Low Power Architecture ......................................... 4 System Integration ................................................ 4 Blackfin Processor Peripherals ................................. 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 6 DMA Controllers ................................................ 10 Real-Time Clock ................................................. 11 Watchdog Timer ................................................ 12 Timers ............................................................. 12 Up/Down Counter and Thumbwheel Interface .......... 12 Serial Ports (SPORTs) .......................................... 12 Serial Peripheral Interface (SPI) Ports ...................... 13 UART Ports (UARTs) .......................................... 13 Controller Area Network (CAN) ...
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... Maximum Core Instruction Rate (MHz) 1 Lockbox is a registered trademark of Analog Devices, Inc. 2 This ROM is not customer-configurable. Specific peripherals for ADSP-BF54x Blackfin processors are shown in Table 2. Specific Peripherals for ADSP-BF54x Processors Module Table 1. EBIU (async) NAND flash controller ATAPI Host DMA port (HOSTDP) ...
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... I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSP- BF54x processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency ...
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... SRAM, and double-rate SDRAM (standard or mobile DDR), optionally accessing up to 768M bytes of physical memory. Most of the ADSP-BF54x Blackfin processors also include an L2 SRAM memory array which provides up to 128K bytes of high speed SRAM, operating at one half the frequency of the core and ...
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... A DMA engine to transfer data between internal memory and a NAND flash device. One-Time-Programmable Memory The ADSP-BF54x Blackfin processors have 64K bits of one- time-programmable (OTP) non-volatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Addi- tionally, its pages can be write protected ...
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... ADSP-BF54x Blackfin processors. Table 3 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 4. System Interrupt Controller (SIC) (Continued) Peripheral IRQ IRQ Source ID DMA6 IRQ (UART0 RX) 14 DMA7 IRQ (UART0 TX) 15 Timer 8 IRQ 16 Timer 9 IRQ 17 Timer 10 IRQ 18 Pin IRQ 0 (PINT0) 19 Pin IRQ 1 (PINT1) 20 MDMA Stream 0 IRQ 21 MDMA Stream 1 IRQ 22 Software Watchdog Timer IRQ ...
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... Pin IRQ 3 (PINT3) 95 Event Control The ADSP-BF54x Blackfin processors provide the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC interrupt latch register (ILAT). The ILAT register indicates when events have been latched ...
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... Host DMA Port Interface The host DMA port (HOSTDP) facilitates a host device external to the ADSP-BF54x Blackfin processors DMA master and transfer data back and forth. The host device always masters the transactions, and the processor is always a DMA slave device. ...
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... SCLK TIMERS There are up to two timer units in the ADSP-BF54x Blackfin processors. One unit provides eight general-purpose program- mable timers, and the other unit provides three. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output input to clock the timer mechanism for measuring pulse widths and peri- ods of external events ...
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... Serial Infrared Physical Layer Link Specification (SIR) protocol. CONTROLLER AREA NETWORK (CAN) The ADSP-BF54x Blackfin processors offer up to two CAN con- trollers that are communication controllers that implement the controller area network (CAN) 2.0B (active) protocol. This pro- tocol is an asynchronous communications protocol used in both industrial and automotive control systems ...
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... Pin Interrupts Every port pin on ADSP-BF54x Blackfin processors can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. Interrupt functionality is decou- pled from GPIO operation. Four system-level interrupt channels (PINT0, PINT1, PINT2 and PINT3) are reserved for this purpose ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The following features are supported in the EPPI module: • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. • Bidirectional and half-duplex port. • Clock can be provided externally or can be generated internally. • Various framed and non-framed operating modes. Frame syncs can be generated internally or can be supplied by an external device ...
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... MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used to wake up the ADSP-BF549 Blackfin processor from the hibernate state. These features allow the ADSP-BF549 processor to operate in a low-power state when there is no network activ- ity or when data is not currently being received or transmitted by the MXVR ...
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... Deep Sleep Operating Mode—Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, 5.0V 600Z ADSP-BF549 10k PG11/MTXON 600Z XN4114 27 PH5/MTX PH6/MRX ...
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... By isolating the inter- nal logic of the ADSP-BF54x Blackfin processors into its own power domain separate from the RTC and other I/O, the pro- cessors can take advantage of dynamic power management without affecting the RTC or other I/O devices ...
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... VCO is always BOOTING MODES The ADSP-BF54x Blackfin processors have many mechanisms (listed in DYNAMIC MODIFICATION nal memory after a reset. The boot mode is specified by four ON-THE-FLY BMODE input pins dedicated to this purpose. There are two categories of boot modes: master and slave. In master boot ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 modes, the processor actively loads data from parallel or serial memories. In slave boot modes, the processor receives data from an external host device. Table 9. Booting Modes BMODE3–0 Description 0000 Idle-no boot 0001 Boot from 8- or 16-bit external flash memory 0010 Boot from 16-bit asynchronous FIFO ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 2 sion 2. multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. • Boot from UART host (BMODE = 0x7)—In this mode, the processor uses UART1 as the booting source. Using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the host. The host agent selects a bit rate within the UART’ ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 By default, the boot kernel will always issue five address cycles; therefore large page device requires only four cycles, the device must be capable of ignoring the additional address cycle. 16-bit NAND flash memory devices must only support the issu- ing of command and address cycles via the lower eight bits of the data bus ...
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... Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS The ADSP-BF54x Blackfin processors are supported with a complete set of CROSSCORE® software and hardware develop- ment tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF54x Blackfin processors ...
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... ADSP-BF549 PH5/MTX pin. • The receive data trace and the transmit data trace between the ADSP-BF549 processor and the FOT should not be routed close to each other in parallel over long distances to avoid crosstalk. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 PIN DESCRIPTIONS ADSP-BF54x Blackfin processors’ pin multiplexing scheme is listed in Table 11 and the pin definitions are listed in Table 11. Pin Multiplexing Primary Pin Function (Number of First Peripheral 1, 2 Pins) Function Port A GPIO (16 pins) SPORT2 (8 pins) SPORT3 (8 pins) Port B GPIO (15 pins) TWI1 (2 pins) ...
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... All port connections always power up as inputs for some period of time and require resistive termination to a safe condition if used as outputs in the system total of 32 interrupts at once are available from ports C through J, configurable in byte-wide blocks. 4 GPW functionality available when MXVR is not present or unused. ADSP-BF54x processor pin definitions are listed in see the pin multiplexing scheme, see Table Table 12. Pin Descriptions Pin Name Port A: GPIO/SPORT2– ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port B: GPIO/TWI1/UART2–3/SPI2/TMR0–3 PB0/SCL1 PB1/SDA1 PB2/UART3RTS PB3/UART3CTS PB4/UART2TX PB5/UART2RX/TACI2 PB6/UART3TX PB7/UART3RX/TACI3 PB8/SPI2SS /TMR0 PB9/SPI2SEL1/TMR1 PB10 SPI2SEL2/TMR2 PB11/SPI2SEL3/TMR3/ HWAIT PB12/SPI2SCK PB13/SPI2MOSI PB14/SPI2MISO Port C: GPIO/SPORT0/SD Controller/MXVR (MOST) PC0/TFS0 PC1/DT0SEC/MMCLK PC2/DT0PRI PC3/TSCLK0 PC4/RFS0 PC5/DR0SEC/MBCLK PC6/DR0PRI PC7/RSCLK0 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port D: GPIO/PPI0–2/SPORT 1/Keypad/Host DMA PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18 PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19 PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20 PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21 PD4/PPI1_D4/HOST_D12/RFS1/PPI0_D22 PD5/PPI1_D5/HOST_D13/DR1SEC/PPI0_D23 PD6/PPI1_D6/HOST_D14/DR1PRI PD7/PPI1_D7/HOST_D15/RSCLK1 PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0 PD9/PPI1_D9/HOST_D1/PPI2_D1/KEY_ROW1 PD10/PPI1_D10/HOST_D2/PPI2_D2/KEY_ROW2 PD11/PPI1_D11/HOST_D3/PPI2_D3/KEY_ROW3 PD12/PPI1_D12/HOST_D4/PPI2_D4/KEY_COL0 PD13/PPI1_D13/HOST_D5/PPI2_D5/KEY_COL1 PD14/PPI1_D14/HOST_D6/PPI2_D6/KEY_COL2 PD15/PPI1_D15/HOST_D7/PPI2_D7/KEY_COL3 Port E: GPIO/SPI0/UART0-1/PPI1/TWI0/Keypad 3 PE0/SPI0SCK/KEY_COL7 3 PE1/SPI0MISO/KEY_ROW6 PE2/SPI0MOSI/KEY_COL6 PE3/SPI0SS/KEY_ROW5 3 PE4/SPI0SEL1/KEY_COL PE5/SPI0SEL2/KEY_ROW4 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port F: GPIO/PPI0/Alternate ATAPI Data PF0/PPI0_D0/ATAPI_D0A PF1/PPI0_D1/ATAPI_D1A PF2/PPI0_D2/ATAPI_D2A PF3/PPI0_D3/ATAPI_D3A PF4/PPI0_D4/ATAPI_D4A PF5/PPI0_D5/ATAPI_D5A PF6/PPI0_D6/ATAPI_D6A PF7/PPI0_D7/ATAPI_D7A PF8/PPI0_D8/ATAPI_D8A PF9/PPI0_D9/ATAPI_D9A PF10/PPI0_D10/ATAPI_D10A PF11/PPI0_D11/ATAPI_D11A PF12/PPI0_D12/ATAPI_D12A PF13/PPI0_D13/ATAPI_D13A PF14/PPI0_D14/ATAPI_D14A PF15/PPI0_D15/ATAPI_D15A Port G: GPIO/PPI0/SPI1/PPI2/Up-Down Counter/CAN0–1/Host DMA/MXVR (MOST)/ATAPI PG0/PPI0_CLK/TMRCLK PG1/PPI0_FS1 PG2/PPI0_FS2/ATAPI_A0A PG3/PPI0_D16/ATAPI_A1A PG4/PPI0_D17/ATAPI_A2A PG5/SPI1SEL1/HOST_CE/PPI2_FS2/CZM PG6/SPI1SEL2/HOST_RD/PPI2_FS1 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port H: GPIO/AMC/EXTDMA/UART1/PPI0–2/ATAPI/Up- Down Counter/TMR8-10/Host DMA/MXVR (MOST) PH0/UART1TX/PPI1_FS3_DEN PH1/UART1RX/PPI0_FS3_DEN/TACI1 PH2/ATAPI_RESET/TMR8/PPI2_FS3_DEN PH3/HOST_ADDR/TMR9/CDG PH4/HOST_ACK/TMR10/CUD PH5/MTX/DMAR0/TACI8 and TACLK8 PH6/MRX/DMAR1/TACI9 and TACLK9 PH7/MRXON/GPW/TACI10 and TACLK10/HWAITA 6 PH8/A4 6 PH9/A5 6 PH10/A6 6 PH11/A7 6 PH12/A8 6 PH13/A9 Port I: GPIO/AMC 6 PI0/A10 6 PI1/A11 6 PI2/A12 6 PI3/A13 6 PI4/A14 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port J: GPIO/AMC/ATAPI PJ0/ARDY/WAIT 7 PJ1/ND_CE PJ2/ND_RB PJ3/ATAPI_DIOR PJ4/ATAPI_DIOW PJ5/ATAPI_CS0 PJ6/ATAPI_CS1 PJ7/ATAPI_DMACK PJ8/ATAPI_DMARQ PJ9/ATAPI_INTRQ PJ10/ATAPI_IORDY 8 PJ11/BR 6 PJ12/BG 6 PJ13/BGH DDR Memory Interface DA0–12 DBA0–1 DQ0–15 DQS0–1 DQM0–1 DCLK0–1 DCLK0–1 DCS0–1 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name High Speed USB OTG Pins USB_DP USB_DM USB_XI USB_XO 10 USB_ID 11 USB_VBUS USB_VREF USB_RSET MXVR (MOST) Interface MFS MLF_P MLF_M MXI MXO Mode Control Pins BMODE0–3 JTAG Port Pins TDI TDO TRST TMS TCK ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name 13 V DDVR GND 12 V DDMP 12 GND Input Output, P =Power Ground Crystal Analog. 2 Refer to Table 61 on Page 86 through Table 70 on Page use the SPI memory boot, SPI0SCK should have a pulldown, SPI0MISO should have a pullup, and SPI0SEL1 is used as the CS with a pullup. ...
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... Bidirectional pins (D15–0, PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0) and input pins (ATAPI_PDIAG, USB_ID, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF54x Blackfin processors are 3.3 V-tolerant (always accept up to 3.6 V maximum V ...
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... Table 13 and Table 16 describe the voltage/frequency require- ments for the ADSP-BF54x Blackfin processors’ clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. describes the phase-locked loop operating conditions. Table 13. Core Clock Requirements—533 MHz and 600 MHz Speed Grade ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ELECTRICAL CHARACTERISTICS Parameter Test Conditions V High Level Output Voltage for 3 High Level Output V 3 Voltage for 2 High Level Output V OHDDR Voltage for DDR SDRAM High Level Output V Voltage for Mobile DDR SDRAM V Low Level Output Voltage for 3 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Parameter Test Conditions I V Current V DD-TYP DDINT f CCLK f SCLK T J ASF = 1. Current V DD-TYP DDINT f CCLK f SCLK T J ASF = 1. Current V DD-TYP DDINT f CCLK f SCLK T J ASF = 1. Current V DD-TYP DDINT f CCLK f SCLK T J ASF = 1.00 13 Hibernate State V DDHIBERNATE Current = 3. CLKIN= 0 MHz with ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 13 See the ADSP-BF54x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 14 Includes current and V DDEXT DDUSB DDVR 15 Guaranteed maximum specifications. is MHz. Example: 1.2 V, 133 MHz would be 0.77 × 1.2 × 133 = 122.9 mA added Unit for (volts) ...
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... DD-TYP I 0.87 DD-APP I 0.74 DD-NOP I 0.47 DD-IDLE 1 See Estimating Power for ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP- BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 processors. Table 20. Dynamic Current in CCLK Domain (mA, with ASF = 1.0) 2 Voltage (V ) DDINT f CCLK 2 (MHz) 0.90 V 0.95 V 1.00 V 100 29 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 21 nent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reli- ability ...
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... PACKAGE INFORMATION The information presented in Figure 9 information related to specific product features. For a complete listing of product offerings, see the Ordering Guide on Page 100. a ADSP-BF54x(M) tppZ-cc vvvvvv.x-q n.n # yywwcountry_of_origin B Figure 9. Product Information on Package Table 24. Package Information Brand Key Description BF54x ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TIMING SPECIFICATIONS Timing specifications are detailed in this section. Clock and Reset Timing Table 25 and Figure 10 describe Clock Input and Reset Timing. Table 26 and Figure 11 describe Clock Out Timing. Table 25. Clock Input and Reset Timing Parameter Timing Requirements CLKIN Period CKIN ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 26. Clock Out Timing Parameter Switching Characteristics 1,2 t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL 1 The t value is the inverse of the f specification. Reduced supply voltages affect the best-case value of 7.5 ns listed here. SCLK SCLK 2 The t value does not account for the effects of jitter. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Asynchronous Memory Read Cycle Timing Table 28 and Table 29 on Page 45 and Figure 13 on Page 45 describe asynchronous memory read cycle opera- tions for synchronous and for asynchronous ARDY. Table 28. Asynchronous Memory Read Cycle Timing with Synchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 29. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Asynchronous Memory Write Cycle Timing Table 30 and Table 31 on Page 47 and Figure 15 on Page 47 describe asynchronous memory write cycle opera- tions for synchronous and for asynchronous ARDY. Table 30. Asynchronous Memory Write Cycle Timing with Synchronous ARDY Parameter Timing Requirements t ARDY Setup Before the Falling Edge of CLKOUT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 31. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t ARDY Negated Delay from AMSx Asserted DANW t ARDY Asserted Hold After AWE Negated HAA Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing Table 32 and Figure 17 describe DDR SDRAM/mobile DDR SDRAM clock and control cycle timing. Table 32. DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing Parameter Switching Characteristics 1 t DCK0-1 Period CK t DCK0-1 High Pulse Width ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR SDRAM/Mobile DDR SDRAM Timing Table 33 and Figure 18/Figure 19 describe DDR SDRAM/mobile DDR SDRAM read cycle timing. Table 33. DDR SDRAM/Mobile DDR SDRAM Read Cycle Timing Parameter Timing Requirements t Access Window of DQ0-15 to DCK0 Access Window of DQS0-1 to DCK0-1 DQSCK t DQS0-1 to DQ0-15 Skew, DQS0-1 to Last ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing Table 34 and Figure 20 describe DDR SDRAM/mobile DDR SDRAM write cycle timing. Table 34. DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing Parameter Switching Characteristics t Write CMD to First DQS0-1 DQSS t DQ0-15/DQM0-1 Setup to DQS0 DQ0-15/DQM0-1 Hold to DQS0-1 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 External Port Bus Request and Grant Cycle Timing Table 35 and Table 36 on Page 52 and Figure 21 on Page 52 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 35. External Port Bus Request and Grant Cycle Timing with Synchronous BR ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 36. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Parameter Timing Requirements t BR Pulsewidth WBR Switching Characteristics t CLKOUT Low to AMSx, Address, and ARE/AWE Disable SD t CLKOUT Low to AMSx, Address, and ARE/AWE Enable SE t CLKOUT Low to BG Asserted Output Delay ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 NAND Flash Controller Interface Timing Table 37 and Figure 23 on Page 54 through Page 56 describe NAND flash controller interface operations. Table 37. NAND Flash Controller Interface Timing Parameter Write Cycle Switching Characteristics t ND_CE Setup Time to AWE Low CWL t ND_CE Hold Time from AWE High ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ND_CE ND_CLE ND_ALE AWE ND_DATA Figure 23. NAND Flash Controller Interface Timing—Command Wri Cycle ND_CE ND_CLE ND_ALE AWE ND_DATA Figure 24. NAND Flash Controller Interface Timing—Address Write Cycle t t CWL CH t CLEWL t ALEWL DWH t DWS In Figure 23, ND_DATA is ND_D0–D15. t CWL ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 t CWL ND_CE t CLEWL ND_CLE t ALEWL ND_ALE AWE DWS ND_DATA In Figure Figure 25. NAND Flash Controller Interface Timing—Data Write Operation t CRL ND_CE ND_CLE ND_ALE ARE DRS ND_DATA In Figure Figure 26. NAND Flash Controller Interface Timing—Data Read Operation Rev Page 55 of 100 | February 2010 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ND_CE ND_CLE AWE ARE ND_DATA Figure 27. NAND Flash Controller Interface Timing—Write Followed by Read Operation t CLWL t t CLEWL CLH WHRL t t DWS DWH In Figure 27, ND_DATA is ND_D0–D15. Rev Page 56 of 100 | February 2010 DRS DRH ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Synchronous Burst AC Timing Table 38 and Figure 28 on Page 57 describe Synchronous Burst AC operations. Table 38. Synchronous Burst AC Timing Parameter Timing Requirements t DATA15-0 Setup Before NR_CLK NDS t DATA15-0 Hold After NR_CLK NDH t WAIT Setup Before NR_CLK NWS t WAIT Hold After NR_CLK NWH Switching Characteristics ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 External DMA Request Timing Table 39 and Figure 29 describe the external DMA request tim- ing operations. Table 39. External DMA Request Timing Parameter Timing Parameters t DMARx Asserted to CLKOUT High Setup DR t CLKOUT High to DMARx Deasserted Hold Time DH t DMARx Active Pulse Width ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Enhanced Parallel Peripheral Interface Timing Table 40 and Figure 32 on Page 60, Figure 30 on Page Figure 33 on Page 60, and Figure 31 on Page 59 enhanced parallel peripheral interface timing operations. Table 40. Enhanced Parallel Peripheral Interface Timing Parameter Timing Requirements t PPIx_CLK Width PCLKW t PPIx_CLK Period PCLK Timing Requirements— ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 FRAME SYNC IS DRIVEN OUT PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 t SDRPE PPI_DATA FRAME SYNC IS DRIVEN OUT PPI_CLK t t HOFSPE PPI_FS1/2 PPI_DATA DATA0 IS SAMPLED t PCLKW t PCLK t HDRPE Figure 32. EPPI GP Rx Mode with Internal Frame Sync Timing DATA0 IS DRIVEN OUT DFSPE t DDTPE Figure 33. EPPI GP Tx Mode with Internal Frame Sync Timing Rev ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Ports Timing Table 41 through Table 44 on Page 63 and through Figure 37 on Page 63 describe serial port operations. Table 41. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TSCLKx (INPUT) TFSx (INPUT) RSCLKx (INPUT) RFSx (INPUT) DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW RSCLKx t DFSI t HOFSI RFSx (OUTPUT) t SFSI RFSx (INPUT) t SDRI DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t SCLKIW TSCLKx t D FSI t HOFSI TFSx (OUTPUT) t SFSI TFSx ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 43. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable Delay from External TSCLKx DTENE t Data Disable Delay from External TSCLKx DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. ...
Page 64
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Peripheral Interface (SPI) Port—Master Timing Table 45 and Figure 38 describe SPI port master operations. Table 45. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SPIxSCK Edge (Data Input Setup) SSPIDM t SPIxSCK Sampling Edge to Data Input Invalid ...
Page 65
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Peripheral Interface (SPI) Port—Slave Timing Table 46 and Figure 39 describe SPI port slave operations. Table 46. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t SPIxSCK High Period SPICHS t SPIxSCK Low Period SPICLS t SPIxSCK Period SPICLK t Last SPIxSCK Edge to SPIxSS Not Asserted ...
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... The UART ports have a maximum baud rate of SCLK/16. There is some latency between the generation of internal UART inter- rupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. For more information, see the ADSP-BF54x Blackfin Processor Hardware Reference. General-Purpose Port Timing Table 47 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Timer Cycle Timing Table 48 and Figure 41 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency of (f /2) MHz. SCLK Table 48. Timer Cycle Timing Parameter Timing Characteristics ...
Page 68
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Up/Down Counter/Rotary Encoder Timing Table 49 and Figure 42 describe up/down counter/rotary encoder timing. Table 49. Up/Down Counter/Rotary Encoder Timing Parameter Timing Requirements t CUD/CDG/CZM Input Pulse Width WCOUNT t CUD/CDG/CZM Input Setup Time Before CLKOUT High CIS t CUD/CDG/CZM Input Hold Time After CLKOUT High ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 SD/SDIO Controller Timing Table 50 and Figure 43 describe SD/SDIO controller timing. Table 51 and Figure 44 describe SD/SDIO controller (high- speed mode) timing. Table 50. SD/SDIO Controller Timing Parameter Timing Requirements t SD_Dx and SD_CMD Input Setup Time ISU t SD_Dx and SD_CMD Input Hold Time ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 51. SD/SDIO Controller Timing (High Speed Mode) Parameter Timing Requirements t SD_Dx and SD_CMD Input Setup Time ISU t SD_Dx and SD_CMD Input Hold Time IH Switching Characteristics f SD_CLK Frequency During Data Transfer Mode PP t SD_CLK Low Time WL t SD_CLK High Time WH t SD_CLK Rise Time ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 MXVR Timing Table 52 and Table 53 describe the MXVR timing requirements. Figure 5 illustrates the MOST connection. Table 52. MXVR Timing—MXI Center Frequency Requirements Parameter f MXI Center Frequency (256 Fs) MXI_256 f MXI Center Frequency (384 Fs) MXI_384 f MXI Center Frequency (512 Fs) MXI_512 f MXI Center Frequency (1024 Fs) MXI_1024 Table 53. MXVR Timing— ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 HOSTDP A/C Timing-Host Read Cycle Table 54 and Figure 45 describe the HOSTDP A/C host read cycle timing requirements. Table 54. Host Read Cycle Timing Requirements Parameter Timing Requirements t HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge SADRDL t HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 HOSTDP A/C Timing-Host Write Cycle Table 55 and Figure 46 describe the HOSTDP A/C host write cycle timing requirements. Table 55. Host Write Cycle Timing Requirements Parameter Timing Requirements t HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge SADWRL t HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge HADWRH ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATA/ATAPI-6 Interface Timing The following tables and figures specify ATAPI timing parame- ters. For detailed parameter descriptions, refer to the ATAPI specification (ANSI INCITS 361-2002). include ATAPI timing parameter equations. System designers should use these equations along with the parameters provided Table 56 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Register and PIO Table 58 and Figure 47 describe the ATAPI register and the PIO data transfer timing. Table 58. ATAPI Register and PIO Data Transfer Timing ATAPI Parameter/Description t Cycle time 0 t ATAPI_ADDR valid to 1 ATAPI_DIOR/ATAPI_DIOW setup t ATAPI_DIOR/ATAPI_DIOW pulse width 2 t ATAPI_DIOR/ATAPI_DIOW recovery time ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATAPI Multiword DMA Transfer Timing Table 59 and Figure 48 through Figure 51 multiword DMA transfer timing. Table 59. ATAPI Multiword DMA Transfer Timing ATAPI Parameter/Description t Cycle time 0 t ATAPI_DIOR/ATAPI_DIOW asserted D Pulse Width t ATAPI_DIOR data hold F t ATAPI_DIOW data setup G(write) t ATAPI_DIOR data setup ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 48 displays the initiation of a multiword DMA data burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A. 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 50 displays a device terminating a multiword DMA data burst. ATAPI_CS0 ATAPI_CS1 ATAPI_DMARQ ATAPI_DMACK ATAPI_DIOR ATAPI_DIOW ATAPI_D0–15 (READ) ATAPI_D0–15 (WRITE) 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATAPI Ultra DMA Data-In Transfer Timing Table 60 and Figure 52 through Figure 55 ultra DMA data-in data transfer timing. Table 60. ATAPI Ultra DMA Data-In Transfer Timing ATAPI Parameter t Data setup time at host DS t Data hold time at host DH t CRC word valid setup time at host ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 52 displays the initiation of an ultra DMA data-in burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A. ATAPI_DMARQ ATAPI_DMACK ATAPI_DIOW ATAPI_DIOR ATAPI_IORDY ATAPI_D0–15 ATAPI ADDR 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 54 displays a device terminating an ultra DMA data-in burst. ATAPI_DMARQ ATAPI_DMACK ATAPI_DIOW ATAPI_DIOR ATAPI_IORDY ATAPI_D0–15 ATAPI ADDR 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATAPI Ultra DMA Data-Out Transfer Timing Table 61 and Figure 56 through Figure 59 ultra DMA data-out transfer timing. Table 61. ATAPI Ultra DMA Data-Out Transfer Timing ATAPI Parameter 2 t Cycle time CYC t Two cycle time 2CYC t Data valid setup time at sender DVS t Data valid hold time at sender ...
Page 83
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 56 displays the initiation of an ultra DMA data-out burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0- 15A. ATAPI_DMARQ ATAPI_DMACK ATAPI_DIOW ATAPI_IORDY ATAPI_DIOR ATAPI_D0–15 ATAPI ADDR 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 58 displays a host terminating an ultra DMA data-out burst. ATAPI_DMARQ ATAPI_DMACK ATAPI_DIOW t SS ATAPI_IORDY ATAPI_DIOR ATAPI_D0–15 ATAPI ADDR 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. ...
Page 85
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 USB On-The-Go-Dual-Role Device Controller Timing Table 62 describes the USB On-The-Go Dual-Role Device Con- troller timing requirements. Table 62. USB On-The-Go Dual-Role Device Controller Timing Requirements Parameter Timing Requirements f USB_XI frequency USB FS USB_XI Clock Frequency Stability USB JTAG Test And Emulation Port Timing ...
Page 86
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 OUTPUT DRIVE CURRENTS Figure 61 through Figure 70 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF54x Blackfin processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 80 2.25V, +105°C 60 2.5V, +25° –20 – ...
Page 87
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 50 2.5V, +105°C 2.6V, +25° –10 –20 –30 VOL –40 2.5V, –105°C 2.6V, +25°C 2.7V, –40°C –50 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 67. Drive Current D (DDR SDRAM) 50 1.875V, +25°C 1.8V, +105° –10 –20 –30 1.8V, +105°C – ...
Page 88
... To determine the data output hold time in a particular system, first calculate the difference between the ADSP-BF54x Blackfin proces- 72). The time, sors’ output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0 ...
Page 89
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 V is equal /2, depending on the pin LOAD DDEXT DDDDR under test. Figure 74 through Figure 85 on Page 91 output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear out- side the ranges shown ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 30 25 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 78. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 2.25 V DDEXT RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 79. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 3.65 V ...
Page 91
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 132 128 124 FALL TIME 120 116 112 108 0 50 100 150 LOAD CAPACITANCE (pF) Figure 84. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver 2.7 V DDEXT 124 120 116 FALL TIME 112 108 104 100 0 50 100 150 LOAD CAPACITANCE (pF) Figure 85 ...
Page 92
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 400-BALL CSP_BGA PACKAGE Table 65 lists the CSP_BGA package by signal for the ADSP-BF549. Table 66 on Page 95 lists the CSP_BGA package by ball number. Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal A1 B2 DA4 A2 A2 DA5 A3 B3 DA6 ABE0 C17 DA7 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal MLF_P E4 PC5 MXI C2 PC6 MXO C1 PC7 NMI C11 PC8 PA0 U12 PC9 PA1 V12 PC10 PA2 W12 PC11 PA3 Y12 PC12 PA4 W11 PC13 PA5 V11 PD0 PA6 Y11 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal TCK V3 V DDDDR TDI V5 V DDDDR TDO V4 V DDDDR TMS U5 V DDDDR TRST T5 V DDEXT USB_DM E2 V DDEXT USB_DP E1 V DDEXT USB_ID G3 V DDEXT USB_RSET D3 V DDEXT USB_VBUS D2 V DDEXT ...
Page 95
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 66 lists the CSP_BGA package by ball number for the ADSP-BF549. Table 65 on Page 92 lists the CSP_BGA package by signal. Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A1 GND PI0 C3 A4 PI2 C4 A5 PI4 C5 A6 PI6 C6 A7 PI8 ...
Page 96
... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. J1 PF1 L1 J2 PC2 L2 J3 PC1 L3 J4 PG0 L4 J5 PC6 DDINT J7 GND L7 J8 GND L8 J9 GND L9 J10 GND L10 J11 GND L11 J12 GND L12 J13 V L13 DDINT ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. U1 PD8 V1 U2 PD9 V2 U3 PD15 V3 U4 PD14 V4 U5 TMS V5 U6 PB3 V6 U7 PB10 V7 U8 GND DDINT U10 PA8 V10 U11 PA7 V11 U12 PA0 V12 U13 PC10 ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 OUTLINE DIMENSIONS Dimensions for the 17 mm × CSP_BGA package in Figure 87 are shown in millimeters. 17.00 BSC SQ A1 BALL INDICATOR TOP VIEW SIDE VIEW 1.70 MAX DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM, WITH THE EXCEPTION OF BALL DIAMETER. ...
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... ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 AUTOMOTIVE PRODUCTS Some ADSP-BF54x Blackfin processor models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. Table 68. Automotive Products 1 Product Family Temperature Range ADBF542WBBCZ-4xx –40°C to +85°C ADBF542WBBCZ-5xx – ...
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... Each ADSP-BF54xM model contains a mobile DDR controller and does not support the use of standard DDR memory RoHS Compliant Part. 3 The ADSP-BF549 is available for automotive use only. Please contact your local ADI product representative or authorized distributor for specific automotive product ordering information. 4 Referenced temperature is ambient temperature. ...