CY7C66113C-PVXC Cypress Semiconductor Corp, CY7C66113C-PVXC Datasheet - Page 37

• Manufacturer Part Number: CY7C66113C-PVXC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-PVXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• No. Of I/o's: 31
• Eeprom Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SSOP
• Supply: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Peripherals: DAC
• Rohs Compliant: Yes
• Controller Family/series: (8051) USB
• Embedded Interface Type: HAPI, I2C, USB
• Processor Series: CY7C66xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1808

USB Upstream Port Status and Control
USB status and control is regulated by the USB Status and Control Register, as shown in
during reset.
USB Status and Control
Bits[2..0]: Control Action
Set to control action as per
the upstream port to be driven manually by firmware. For normal
USB operation, all of these bits must be cleared.
how the control bits affect the upstream port.
Table 13. Control Bit Definition for Upstream Port
Bit 3: Bus Activity
This is a “sticky” bit that indicates if any non idle USB event has
occurred on the upstream USB port. Firmware should check and
clear this bit periodically to detect any loss of bus activity. Writing
a ‘0’ to the Bus Activity bit clears it, while writing a ‘1’ preserves
the current value. In other words, the firmware clears the Bus
Activity bit, but only the SIE can set it.
Bits 4 and 5: D– Upstream and D+ Upstream
These bits give the state of each upstream port pin individually:
1 = HIGH, 0 = LOW.
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
Control Bits
000
001
010
011
100
101
110
7
Endpoint
Size
R/W
0
111
Table
6
Endpoint
Mode
0
R/W
13.The three control bits allow
Not Forcing (SIE Controls Driver)
Force D+[0] HIGH, D–[0] LOW
Force D+[0] LOW, D–[0] HIGH
Force SE0; D+[0] LOW, D–[0] LOW
Force D+[0] LOW, D–[0] LOW
Force D+[0] HiZ, D–[0] LOW
Force D+[0] LOW, D–[0] HiZ
Force D+[0] HiZ, D–[0] HiZ
Figure 42. USB Status and Control Register
5
D+
Upstream
0
R
Table 13
shows
4
D– Upstream Bus Activity
R
0
Bit 6: Endpoint Mode
This bit used to configure the number of USB endpoints. See
USB Device Endpoints
Bit 7: Endpoint Size
This bit used to configure the number of USB endpoints. See
USB Device Endpoints
The hub generates an EOP at EOF1 in accordance with the USB
1.1 Specification, Section 11.2.2.
3
R/W
0
Control Action
CY7C66013C, CY7C66113C
Figure
2
Control
Action
Bit 2
R/W
0
for a detailed description.
for a detailed description.
42. All bits in the register are cleared
1
Control
Action
Bit 1
R/W
0
ADDRESS
Page 37 of 59
0
Control
Action
Bit 0
R/W
0
0x1F
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