CY7C64713-56LTXC Cypress Semiconductor Corp, CY7C64713-56LTXC Datasheet - Page 46

• Manufacturer Part Number: CY7C64713-56LTXC
• Description: IC MCU USB PHERIPH FX1 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LTXC

• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2929

Although there are no specific timing requirement for asserting
PKTEND, there is a specific corner case condition that needs
attention while using the PKTEND to commit a one byte or word
packet. Additional timing requirements exist when the FIFO is
configured to operate in auto mode and it is necessary to send
two packets: a full packet (full defined as the number of bytes in
the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 33
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
■
■
Document #: 38-08039 Rev. *F
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of t
t
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
RDpwh
FIFOADR
FLAGS
FIFO DATA BUS Not Driven
DATA
FIFO POINTER
SLRD
SLCS
SLOE
. If SLCS is used then, SLCS must be in asserted with
shows the timing relationship of the SLAVE FIFO
RDpwl
t=0
t=1
N
Driven
Data (X)
and minimum de-active pulse width of
t
SFA
t
OEon
SLOE
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t=2
Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram
t
RDpwl
Driven: X
t
XFD
t=3
N
N
t=4
t
RDpwh
t
FAH
SLRD
t
OEoff
t
XFLG
N
N
SLRD
T=0
N+1
T=1
N
SLOE
t
t
SFA
OEon
N
T=2
Not Driven
t
N+1
RDpwl
t
XFD
T=3
SLOE
packet committed manually using the PKTEND pin. In this case,
the external master must make sure to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte or word to be clocked into the previous auto committed
packet (the packet with the number of bytes equal to what is set
in the AUTOINLEN register). Refer to
further details on this timing.
■
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After the SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is incre-
mented.
The data that drives after asserting SLRD, is the updated data
from the FIFO. This data is valid after a propagation delay of
t
the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is, SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
t
N+1
XFD
RDpwh
N+1
N
from the activating edge of SLRD. In
T=4
SLRD
t
RDpwl
t
XFD
N+1
T=5
N+1
SLRD
t
N+2
RDpwh
T=6
N+2
N+1
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
T=7
t
t
RDpwh
FAH
SLRD
t
OEoff
t
Table 20
XFLG
N+3
N+2
Figure
CY7C64713
SLOE
on page 39 for
Page 46 of 55
33, data N is
Not Driven
N+3
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