CY7C64713-100AXC Cypress Semiconductor Corp, CY7C64713-100AXC Datasheet - Page 34

• Manufacturer Part Number: CY7C64713-100AXC
• Description: IC MCU USB EZ FX1 16KB 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-100AXC

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1679; CY7C64713-100AXC

Table 13. Data Memory Write Parameters
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document #: 38-08039 Rev. *F
t
t
t
t
t
t
AV
STBL
STBH
SCSL
ON1
OFF1
Parameter
CLKOUT
CLKOUT
A[15..0]
A[15..0]
D[7..0]
D[7..0]
CS#
WR#
CS#
WR#
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
Clock to Data Hold Time
t
t
AV
AV
t
t
CL
CL
t
SCSL
t
ON1
t
ON1
Description
t
STBL
Figure 14. Data Memory Write Timing Diagram
data out
Stretch = 1
data out
t
STBH
Min
0
0
0
0
0
t
t
OFF1
AV
Max
10.7
13.0
13.1
11.2
11.2
13.1
Unit
ns
ns
ns
ns
ns
ns
CY7C64713
t
OFF1
Notes
Page 34 of 55
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