CY7C64713-100AXC Cypress Semiconductor Corp, CY7C64713-100AXC Datasheet - Page 45
![IC MCU USB EZ FX1 16KB 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C64713-100AXC
Manufacturer Part Number
CY7C64713-100AXC
Description
IC MCU USB EZ FX1 16KB 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX1™r
Datasheet
1.CY7C64713-56LTXC.pdf
(55 pages)
Specifications of CY7C64713-100AXC
Program Memory Type
ROMless
Package / Case
100-LQFP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C647xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
40
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Processor Series
CY7C64xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3674
Minimum Operating Temperature
0 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
40
Ram Memory Size
256Byte
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1679
CY7C64713-100AXC
CY7C64713-100AXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C64713-100AXC
Manufacturer:
SST
Quantity:
230
Company:
Part Number:
CY7C64713-100AXC
Manufacturer:
CY
Quantity:
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Company:
Part Number:
CY7C64713-100AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C64713-100AXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when
SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the
FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is
asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.
Single and Burst Synchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 32
signals during a synchronous write using IFCLK as the synchro-
nizing clock. This diagram illustrates a single write followed by
burst write of 3 bytes and committing all 4 bytes as a short packet
using the PKTEND pin.
■
■
■
■
Document #: 38-08039 Rev. *F
Note t
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
At t = 1, the external master or peripheral must output the data
value onto the data bus with a minimum set up time of t
before the rising edge of IFCLK.
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of t
edge of IFCLK) and maintain a minimum hold time of t
from the IFCLK edge to the deassertion of the SLWR signal).
If SLCS signal is used, it must be asserted with SLWR or before
SLWR is asserted. (that is the SLCS and SLWR signals must
both be asserted to start a valid write condition).
While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
PKTEND
FIFOADR
FLAGS
DATA
IFCLK
SLWR
SLCS
SFA
SWR
shows the timing relationship of the SLAVE FIFO
has a minimum of 25 ns. This means when IFCLK is
(time from asserting the SLWR signal to the rising
t=0
Figure 32. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
SFA
t=1
t=2
t
t
SFD
SWR
t
N
IFCLK
t=3
t
FDH
t
WRH
t
XFLG
t
FAH
WRH
SFD
(time
T=0
t
SFA
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In
SLWR is deasserted. The short 4-byte packet is committed to the
host by asserting the PKTEND signal.
There is no specific timing requirement that must be met for
asserting the PKTEND signal with regards to asserting the
SLWR signal. PKTEND is asserted with the last data value or
thereafter. The only consideration is the setup time t
hold time t
number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND is asserted in subsequent clock cycles. The
FIFOADDR lines must be held constant during the PKTEND
assertion.
T=1
The FIFO flag is also updated after a delay of t
rising edge of the clock.
T=2
>= t
t
SFD
SWR
N+1
Figure
PEH
t
FDH
T=3
must be met. In the scenario of
32, after the four bytes are written to the FIFO,
t
SFD
N+2
t
FDH
T=4
t
SFD
t
N+3
SPE
>= t
t
t
XFLG
FDH
T=5
t
WRH
PEH
CY7C64713
t
FAH
XFLG
Figure
Page 45 of 55
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