CY7C68014A-100AXC Cypress Semiconductor Corp, CY7C68014A-100AXC Datasheet - Page 40
![IC MCU USB PERIPH HI SPD 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C68014A-100AXC
Manufacturer Part Number
CY7C68014A-100AXC
Description
IC MCU USB PERIPH HI SPD 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68014A-100AXC
Program Memory Type
ROMless
Package / Case
100-LQFP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
40
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
0 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
40
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Package
100TQFP
Device Core
8051
Family Name
FX2LP
Maximum Speed
48 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1670
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68014A-100AXC
Manufacturer:
Cypress Semiconductor
Quantity:
135
Company:
Part Number:
CY7C68014A-100AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C68014A-100AXC
Manufacturer:
CYRUSTEK
Quantity:
20 000
10.4 Data Memory Write
Table 17. Data Memory Write Parameters
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
AV
STBL
STBH
SCSL
ON1
OFF1
CLKOUT
CLKOUT
Parameter
A[15..0]
A[15..0]
D[7..0]
D[7..0]
CS#
WR#
CS#
WR#
t
t
AV
AV
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
Clock to Data Hold Time
t
t
CL
CL
t
SCSL
t
ON1
t
ON1
t
STBL
Description
Figure 14. Data Memory Write Timing Diagram
data out
Stretch = 1
data out
t
STBH
Min
0
0
0
0
0
t
t
OFF1
AV
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Max
10.7
13.0
13.1
11.2
11.2
13.1
Unit
ns
ns
ns
ns
ns
ns
Page 40 of 62
t
OFF1
Notes
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