CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 30

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

Table 12. FX2LP Register Summary (continued)
Document #: 38-08032 Rev. *M
Hex
E62B 1
E62C 1
E62D 1
E62E 1
E62F 1
E630
H.S.
E630
F.S.
E631
H.S.
E631
F.S
E632
H.S.
E632
F.S
E633
H.S.
E633
F.S
E634
H.S.
E634
F.S
E635
H.S.
E635
F.S
E636
H.S.
E636
F.S
E637
H.S.
E637
F.S
E640 1
E641 1
E642 1
E643 1
E644 4
E648 1
E649 7
E650 1
E651 1
E652 1
E653 1
E654 1
E655 1
E656 1
E657 1
E658 1
E659 1
E65A 1
E65B 1
E65C 1
Note
12. The register can only be reset, it cannot be set.
Size Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
ECC1B1
ECC1B2
ECC2B0
ECC2B1
ECC2B2
EP2FIFOPFH
EP2FIFOPFH
EP2FIFOPFL
EP2FIFOPFL
EP4FIFOPFH
EP4FIFOPFH
EP4FIFOPFL
EP4FIFOPFL
EP6FIFOPFH
EP6FIFOPFH
EP6FIFOPFL
EP6FIFOPFL
EP8FIFOPFH
EP8FIFOPFH
EP8FIFOPFL
EP8FIFOPFL
reserved
EP2ISOINPKTS
EP4ISOINPKTS
EP6ISOINPKTS
EP8ISOINPKTS
reserved
INPKTEND
OUTPKTEND
INTERRUPTS
EP2FIFOIE
EP2FIFOIRQ
EP4FIFOIE
EP4FIFOIRQ
EP6FIFOIE
EP6FIFOIRQ
EP8FIFOIE
EP8FIFOIRQ
IBNIE
IBNIRQ
NAKIE
NAKIRQ
USBIE
[12]
[12]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11,12]
[11,12]
[11,12]
[11,12]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
Description
ECC1 Byte 1 Address
ECC1 Byte 2 Address
ECC2 Byte 0 Address
ECC2 Byte 1 Address
ECC2 Byte 2 Address
Endpoint 2 / slave FIFO
Programmable Flag H
Endpoint 2 / slave FIFO
Programmable Flag H
Endpoint 2 / slave FIFO
Programmable Flag L
Endpoint 2 / slave FIFO
Programmable Flag L
Endpoint 4 / slave FIFO
Programmable Flag H
Endpoint 4 / slave FIFO
Programmable Flag H
Endpoint 4 / slave FIFO
Programmable Flag L
Endpoint 4 / slave FIFO
Programmable Flag L
Endpoint 6 / slave FIFO
Programmable Flag H
Endpoint 6 / slave FIFO
Programmable Flag H
Endpoint 6 / slave FIFO
Programmable Flag L
Endpoint 6 / slave FIFO
Programmable Flag L
Endpoint 8 / slave FIFO
Programmable Flag H
Endpoint 8 / slave FIFO
Programmable Flag H
Endpoint 8 / slave FIFO
Programmable Flag L
Endpoint 8 / slave FIFO
Programmable Flag L
EP2 (if ISO) IN Packets
per frame (1-3)
EP4 (if ISO) IN Packets
per frame (1-3)
EP6 (if ISO) IN Packets
per frame (1-3)
EP8 (if ISO) IN Packets
per frame (1-3)
Force IN Packet End
Force OUT Packet End
Endpoint 2 slave FIFO
Flag Interrupt Enable
Endpoint 2 slave FIFO
Flag Interrupt Request
Endpoint 4 slave FIFO
Flag Interrupt Enable
Endpoint 4 slave FIFO
Flag Interrupt Request
Endpoint 6 slave FIFO
Flag Interrupt Enable
Endpoint 6 slave FIFO
Flag Interrupt Request
Endpoint 8 slave FIFO
Flag Interrupt Enable
Endpoint 8 slave FIFO
Flag Interrupt Request
IN-BULK-NAK Interrupt
Enable
IN-BULK-NAK interrupt
Request
Endpoint Ping-NAK / IBN
Interrupt Enable
Endpoint Ping-NAK / IBN
Interrupt Request
USB Int Enables
b7
LINE7
COL5
LINE15
LINE7
COL5
DECIS
DECIS
PFC7
IN:PKTS[1]
OUT:PFC7
DECIS
DECIS
PFC7
IN: PKTS[1]
OUT:PFC7
DECIS
DECIS
PFC7
IN:PKTS[1]
OUT:PFC7
DECIS
DECIS
PFC7
IN: PKTS[1]
OUT:PFC7
AADJ
AADJ
AADJ
AADJ
Skip
Skip
0
0
0
0
0
0
0
0
0
0
EP8
EP8
0
b6
LINE6
COL4
LINE14
LINE6
COL4
PKTSTAT
PKTSTAT
PFC6
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PKTSTAT
PFC6
IN: PKTS[0]
OUT:PFC6
PKTSTAT
PKTSTAT
PFC6
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PKTSTAT
PFC6
IN: PKTS[0]
OUT:PFC6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EP6
EP6
EP0ACK
b5
LINE5
COL3
LINE13
LINE5
COL3
IN:PKTS[2]
OUT:PFC12
OUT:PFC12 OUT:PFC11 OUT:PFC10 0
PFC5
PFC5
0
0
PFC5
PFC5
IN:PKTS[2]
OUT:PFC12
OUT:PFC12 OUT:PFC11 OUT:PFC10 0
PFC5
PFC5
0
0
PFC5
PFC5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EP8
EP8
EP4
EP4
HSGRANT
b4
LINE4
COL2
LINE12
LINE4
COL2
IN:PKTS[1]
OUT:PFC11
PFC4
PFC4
IN: PKTS[1]
OUT:PFC10
OUT:PFC10 OUT:PFC9 0
PFC4
PFC4
IN:PKTS[1]
OUT:PFC11
PFC4
PFC4
IN: PKTS[1]
OUT:PFC10
OUT:PFC10 OUT:PFC9 0
PFC4
PFC4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EP6
EP6
EP2
EP2
URES
b3
LINE3
COL1
LINE11
LINE3
COL1
IN:PKTS[0]
OUT:PFC10
PFC3
PFC3
IN: PKTS[0]
OUT:PFC9
PFC3
PFC3
IN:PKTS[0]
OUT:PFC10
PFC3
PFC3
IN: PKTS[0]
OUT:PFC9
PFC3
PFC3
0
0
0
0
EP3
EP3
EDGEPF
0
EDGEPF
0
EDGEPF
0
EDGEPF
0
EP4
EP4
EP1
EP1
SUSP
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
b2
LINE2
COL0
LINE10
LINE2
COL0
0
PFC2
PFC2
0
PFC2
PFC2
0
PFC2
PFC2
0
PFC2
PFC2
0
0
0
0
EP2
EP2
PF
PF
PF
PF
PF
PF
PF
PF
EP2
EP2
EP0
EP0
SUTOK
b1
LINE1
LINE17
LINE9
LINE1
0
PFC9
PFC9
PFC1
PFC1
0
0
PFC1
PFC1
PFC9
PFC9
PFC1
PFC1
0
0
PFC1
PFC1
INPPF1
INPPF1
INPPF1
INPPF1
EP1
EP1
EF
EF
EF
EF
EF
EF
EF
EF
EP1
EP1
0
0
SOF
b0
LINE0
LINE16
LINE8
LINE0
0
PFC8
IN:PKTS[2]
OUT:PFC8
PFC0
PFC0
PFC8
PFC8
PFC0
PFC0
PFC8
IN:PKTS[2]
OUT:PFC8
PFC0
PFC0
PFC8
PFC8
PFC0
PFC0
INPPF0
INPPF0
INPPF0
INPPF0
EP0
EP0
FF
FF
FF
FF
FF
FF
FF
FF
EP0
EP0
IBN
IBN
SUDAV
Page 30 of 62
Default
00000000 R
00000000 R
00000000 R
00000000 R
00000000 R
10001000 bbbbbrbb
10001000 bbbbbrbb
00000000 RW
00000000 RW
10001000 bbrbbrrb
10001000 bbrbbrrb
00000000 RW
00000000 RW
00001000 bbbbbrbb
00001000 bbbbbrbb
00000000 RW
00000000 RW
00001000 bbrbbrrb
00001000 bbrbbrrb
00000000 RW
00000000 RW
00000001 brrrrrbb
00000001 brrrrrrr
00000001 brrrrrbb
00000001 brrrrrrr
xxxxxxxx W
xxxxxxxx W
00000000 RW
00000000 rrrrrbbb
00000000 RW
00000000 rrrrrbbb
00000000 RW
00000000 rrrrrbbb
00000000 RW
00000000 rrrrrbbb
00000000 RW
00xxxxxx rrbbbbbb
00000000 RW
xxxxxx0x bbbbbbrb
00000000 RW
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