CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 33

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

Table 12. FX2LP Register Summary (continued)
Document #: 38-08032 Rev. *M
Hex
E6CB 1
E6CC 1
E6CD 1
E6CE 1
E6CF 1
E6D0 1
E6D1 1
E6D2 1
E6D3 1
E6D4 1
E6DA 1
E6DB 1
E6DC 1
E6E2 1
E6E3 1
E6E4 1
E6EA 1
E6EB 1
E6EC 1
E6F0 1
E6F1 1
E6F2 1
E6F3 1
E6F4 1
E6F5 1
E6F6 2
E740 64
E780 64
E7C0 64
E800 2048 reserved
F000 1024 EP2FIFOBUF
F400 512 EP4FIFOBUF
F600 512 reserved
F800 1024 EP6FIFOBUF
FC00 512 EP8FIFOBUF
FE00 512 reserved
Size Name
2
3
3
3
3
FLOWSTB
FLOWSTBEDGE
FLOWSTBPERIOD
GPIFTCB3
GPIFTCB2
GPIFTCB1
GPIFTCB0
reserved
reserved
reserved
EP2GPIFFLGSEL
EP2GPIFPFSTOP
EP2GPIFTRIG
reserved
reserved
reserved
EP4GPIFFLGSEL
EP4GPIFPFSTOP
EP4GPIFTRIG
reserved
reserved
reserved
EP6GPIFFLGSEL
EP6GPIFPFSTOP
EP6GPIFTRIG
reserved
reserved
reserved
EP8GPIFFLGSEL
EP8GPIFPFSTOP
EP8GPIFTRIG
reserved
XGPIFSGLDATH
XGPIFSGLDATLX
XGPIFSGLDATL-
NOX
GPIFREADYCFG
GPIFREADYSTAT
GPIFABORT
reserved
ENDPOINT BUFFERS
EP0BUF
EP10UTBUF
EP1INBUF
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
Description
Flowstate Strobe
Configuration
Flowstate Rising/Falling
Edge Configuration
Master-Strobe Half-Period D7
GPIF Transaction Count
Byte 3
GPIF Transaction Count
Byte 2
GPIF Transaction Count
Byte 1
GPIF Transaction Count
Byte 0
Endpoint 2 GPIF Flag
select
Endpoint 2 GPIF stop
transaction on prog. flag
Endpoint 2 GPIF Trigger x
Endpoint 4 GPIF Flag
select
Endpoint 4 GPIF stop
transaction on GPIF Flag
Endpoint 4 GPIF Trigger x
Endpoint 6 GPIF Flag
select
Endpoint 6 GPIF stop
transaction on prog. flag
Endpoint 6 GPIF Trigger x
Endpoint 8 GPIF Flag
select
Endpoint 8 GPIF stop
transaction on prog. flag
Endpoint 8 GPIF Trigger x
GPIF Data H
(16-bit mode only)
Read/Write GPIF Data L &
trigger transaction
Read GPIF Data L, no
transaction trigger
Internal RDY, Sync/Async,
RDY pin states
GPIF Ready Status
Abort GPIF Waveforms
EP0-IN/-OUT buffer
EP1-OUT buffer
EP1-IN buffer
512/1024 byte EP 2 / slave
FIFO buffer (IN or OUT)
512 byte EP 4 / slave FIFO
buffer (IN or OUT)
512/1024 byte EP 6 / slave
FIFO buffer (IN or OUT)
512 byte EP 8 / slave FIFO
buffer (IN or OUT)
b7
SLAVE
0
TC31
TC23
TC15
TC7
0
0
0
0
0
0
0
0
D15
D7
D7
INTRDY
0
x
D7
D7
D7
D7
D7
D7
D7
b6
RDYASYNC CTLTOGL
0
D6
TC30
TC22
TC14
TC6
0
0
x
0
0
x
0
0
x
0
0
x
D14
D6
D6
SAS
0
x
D6
D6
D6
D6
D6
D6
D6
b5
0
D5
TC29
TC21
TC13
TC5
0
0
x
0
0
x
0
0
x
0
0
x
D13
D5
D5
TCXRDY5
RDY5
x
D5
D5
D5
D5
D5
D5
D5
b4
SUSTAIN
0
D4
TC28
TC20
TC12
TC4
0
0
x
0
0
x
0
0
x
0
0
x
D12
D4
D4
0
RDY4
x
D4
D4
D4
D4
D4
D4
D4
b3
0
0
D3
TC27
TC19
TC11
TC3
0
0
x
0
0
x
0
0
x
0
0
x
D11
D3
D3
0
RDY3
x
D3
D3
D3
D3
D3
D3
D3
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
b2
MSTB2
0
D2
TC26
TC18
TC10
TC2
0
0
x
0
0
x
0
0
x
0
0
x
D10
D2
D2
0
RDY2
x
D2
D2
D2
D2
D2
D2
D2
b1
MSTB1
FALLING
D1
TC25
TC17
TC9
TC1
FS1
0
x
FS1
0
x
FS1
0
x
FS1
0
x
D9
D1
D1
0
RDY1
x
D1
D1
D1
D1
D1
D1
D1
b0
MSTB0
RISING
D0
TC24
TC16
TC8
TC0
FS0
FIFO2FLAG 00000000 RW
x
FS0
FIFO4FLAG 00000000 RW
x
FS0
FIFO6FLAG 00000000 RW
x
FS0
FIFO8FLAG 00000000 RW
x
D8
D0
D0
0
RDY0
x
D0
D0
D0
D0
D0
D0
D0
Page 33 of 62
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