CY8C20546A-24PVXI Cypress Semiconductor Corp, CY8C20546A-24PVXI Datasheet - Page 3
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CY8C20546A-24PVXI
Manufacturer Part Number
CY8C20546A-24PVXI
Description
IC MCU 16K FLASH 2K SRAM 48SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CapSense® Controllersr
Datasheet
1.CY8C20536A-24PVXI.pdf
(38 pages)
Specifications of CY8C20546A-24PVXI
Program Memory Type
FLASH (16 kB)
Package / Case
48-SSOP
Applications
Capacitive Sensing
Core Processor
M8C
Controller Series
CY8C20xx6A
Ram Size
2K x 8
Interface
I²C, SPI
Number Of I /o
36
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8C20x46A
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
31
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3280-20X66
Minimum Operating Temperature
- 40 C
Program Memory Size
16 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C20546A-24PVXI
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CY8C20546A-24PVXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
PSoC
The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The architecture for this device family, as shown in the
Block Diagram on page
Core, the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between I/O and the analog system. Each
CY8C20x36A/46A/66A/96A PSoC Device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 general purpose IO (GPIO) are also
included. The GPIO provides access to the MCU and analog
mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard archi-
tecture microprocessor.
System Resources provide additional capability, such as
configurable
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
Document Number: 001-54459 Rev. **
®
Functional Overview
USB
and
2, is comprised of three main areas: the
I2C
slave/SPI
master-slave
Logic
Figure 1. Analog System Block Diagram
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under
Documentation > Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Complex capacitive sensing interfaces, such as sliders and
touchpads.
Chip-wide mux that allows analog input from any I/O pin.
Crosspoint connection between any I/O pin combinations.
Vr
IMO
Comparator
IDAC
Reference
Buffer
Clock Select
CapSense
CY8C20X36A/46A/66A/96A
Cap Sense Counters
CSCLK
Mux
Mux
Refs
Oscillator
http://www.cypress.com
Cinternal
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