Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 26

• Manufacturer Part Number: Z9025106PSG
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSG

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
Note:
Note:
Note:
The Z90255 and Z90251 have Stop-Mode Recovery (SMR) circuitry. Two SMR
methods are implemented, a single-fixed input pin or a flexible, programmable set
of inputs. The Z8-base product specification should be reviewed to determine the
SMR options available.
In simple cases, a Low level applied to input pin P27 triggers an SMR. To use this
mode, pin P27 (I/O Port 2, bit 7) must be configured as an input before entering
Stop Mode. The Low level on P27 must meet a minimum pulse width TWSM.
Some microcontrollers provide multiple SMR input sources. The SMR source is
selected via the SMR Register.
STOP Mode Recovery Register
The STOP Mode Recovery Register register selects the clock divide value and
determines the mode of Stop Mode Recovery. All bits are Write-Only, except bit 7
which is Read-Only. Bit 7 is a flag bit that is hardware set in a Stop Mode
Recovery condition, and reset by a power-on cycle. Bit 6 controls whether a Low
level or a High level is required from the recovery source. Bit 5 controls the reset
delay after recovery. Bits 2, 3, and 4, of the SMR register, specify the source of the
Stop-Mode Recovery signal. Bits 0 and 1 control internal clock divider circuitry.
The SMR is located in bank F of the expanded register file at address 0Bh.
Table 6 contains Stop Mode Recovery (SMR) Register bit descriptions.
Stop-Mode Recovery (SMR) by the WDT increases the Stop
Mode standby current (ICC2). This is because the internal RC
oscillator is running to support this recovery mode.
Using specialized SMR modes (P27 input or SMR register
based) or the WDT timeout (only when in the Stop Mode)
provides a unique reset operation. Some control registers are
initialized differently for a SMR/WDT triggered POR than a
standard reset operation.
The Stop Mode current (ICC2) is minimized when
- V
- WDT is Off in Stop Mode
- Output current sourcing is minimized
- All inputs (digital and analog) are at the low or high rail voltages
CC
is at the low end of the device operating range
32 KB Television Controller with OSD
PS001301-0800
18