CY7C63001A-SC Cypress Semiconductor Corp, CY7C63001A-SC Datasheet - Page 10

• Manufacturer Part Number: CY7C63001A-SC
• Description: IC MCU 4K LS USB MCU 20-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001A-SC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1313

Writing a “0” to the Data Register drives the output LOW.
Instead of providing a fixed output drive, the USB Controller
allows the user to select an output sink current level for each
I/O pin. The sink current of each output is controlled by a
Port 0 is a low-current port suitable for connecting photo
transistors. Port 1 is a high current port capable of driving
LEDs. See section 8.0 for current ranges. 0000 is the lowest
drive strength. 1111 is the highest.
The write-only sink current control registers for Port 0 outputs
are assigned from I/O address 0x30 to 0x37 with the control
bits for P00 starting at 0x30. Port 1 sink current control
registers are assigned from I/O address 0x38 to 0x3F with the
control bits for P10 starting at 0x38. All sink current control
6.8
Interrupts are generated by the General Purpose I/O lines, the
Cext pin, the internal timer, and the USB engine. All interrupts
are maskable by the Global Interrupt Enable Register. Access
to this register is accomplished via IORD, IOWR, and IOWX
The interrupt controller contains a separate latch for each
interrupt. See Figure 6-16 for the logic block diagram for the
interrupt controller. When an interrupt is generated, it is
latched as a pending interrupt. It stays as a pending interrupt
until it is serviced or a reset occurs. A pending interrupt only
Document #: 38-08026 Rev. *A
Reserved
PULL1.7
CEXTIE
R/W
b7
b7
b7
0x
W
W
x
0
Interrupts
(to Microcontroller)
(to USB SIE)
Reserved
PULL1.6
GPIOIE
R/W
clk1x
clk2x
b6
b6
b6
W
W
0
0
x
Figure 6-15. Global Interrupt Enable Register (GIER – Address 0x20)
Reserved
Reserved
PULL1.5
Figure 6-12. Port 1 Pull-up Register (Address 0x09)
Figure 6-13. Port Isink Register for One GPIO Line
b5
b5
b5
W
W
0
x
0
Figure 6-14. Clock Oscillator On-chip Circuit
Doubler
Clock
UNUSED
PULL1.4
EP1IE
R/W
b4
b4
b4
W
W
0
x
0
30 pF
dedicated Port Isink Register. The lower four bits of this
register contain a code selecting one of sixteen sink current
levels. The upper four bits of the register are ignored. The
format of the Port Isink Register is shown in Figure 6-13.
registers are cleared during a reset, resulting in the minimum
current sink setting.
6.7
The XTALIN and XTALOUT pins support connection of a 6-
MHz ceramic resonator. The feedback capacitors and bias
resistor are internal to the IC, as shown in Figure 6-14 Leave
XTALOUT unconnected when driving XTALIN from an external
oscillator.
instructions to address 0x20. Writing a “1” to a bit position
enables the interrupt associated with that position. During a
reset, the contents of the Interrupt Enable Register are
cleared, disabling all interrupts. Figure 6-15 illustrates the
format of the Global Interrupt Enable Register.
generates an interrupt request if it is enabled in the Global
Interrupt Enable Register. The highest priority interrupt
request is serviced following the execution of the current
instruction.
PULL1.3
ISINK3
EP0IE
R/W
b3
b3
b3
W
W
0
0
x
XTALIN/XTALOUT
30 pF
PULL1.2
ISINK2
1024IE
R/W
b2
b2
b2
W
W
0
x
0
PULL1.1
ISINK1
XTALOUT
XTALIN
128IE
R/W
b1
b1
b1
W
W
0
x
0
CY7C63001A
CY7C63101A
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Reserved
PULL1.0
ISINK0
b0
b0
b0
W
W
0
0
x