CY7C63413-PC Cypress Semiconductor Corp, CY7C63413-PC Datasheet - Page 16

• Manufacturer Part Number: CY7C63413-PC
• Description: IC MCU 8K USB LS PERIPH 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1318

provides “HIGH” source current when the GPIO port is configured for CMOS outputs and the output data bit is written as a “1”.
Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of current to support traditional CMOS outputs
with symmetric drive.
Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured as inputs with internal pull-ups, open drain outputs, or traditional
CMOS outputs. An open drain output is also a high-impedance input. Port 3 offers high current drive with a typical current sink
capability of 12 mA. The internal pull-up resistors are typically 7 Kohms.
During reset, all of the GPIO pins are set to output “1” (input) with the internal pull-up enabled. In this state, a “1” will always be
read on that GPIO pin unless an external current sink drives the output to a “0” state. Writing a “0” to a GPIO pin enables the
output current sink to ground (LOW) and disables the internal pull-up for that pin.
9.1
During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a “1” to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input pin.
9.2
Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In ad-
dition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising edge (“0” to “1”) on an input
pin causes an interrupt. With negative polarity, a falling edge (“1” to “0”) on an input pin causes an interrupt. As shown in the table
below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. The GPIO Configuration Port
register provides two bits per port to program these features. The possible port configurations are:
P0[7]
P1[7]
P2[7]
P3[7]
P0[7]
P1[7]
P2[7]
P3[7]
GPIO Interrupt Enable Ports
GPIO Configuration Port
P0[6]
P1[6]
P2[6]
P3[6]
P0[6]
P1[6]
P2[6]
P3[6]
Figure 9-6. Port 0 Interrupt Enable 0x04h (write only)
Figure 9-7. Port 1 Interrupt Enable 0x05h (write only)
Figure 9-8. Port 2 Interrupt Enable 0x06h (write only)
Figure 9-9. Port 3 Interrupt Enable 0x07h (write only)
P0[5]
P1[5]
P2[5]
P3[5]
P0[5]
P1[5]
P2[5]
P3[5]
Figure 9-2. Port 0 Data 0x00h (read/write)
Figure 9-3. Port 1 Data 0x01h (read/write)
Figure 9-4. Port 2 Data 0x02h (read/write)
Figure 9-5. Port 3 Data 0x03h (read/write)
P0[4]
P1[4]
P2[4]
P3[4]
P0[4]
P1[4]
P2[4]
P3[4]
16
P0[3]
P1[3]
P2[3]
P3[3]
P0[3]
P1[3]
P2[3]
P3[3]
P0[2]
P1[2]
P2[2]
P3[2]
P0[2]
P1[2]
P2[2]
P3[2]
CY7C63411/12/13
CY7C63511/12/13
P0[1]
P1[1]
P2[1]
P3[1]
P0[1]
P1[1]
P2[1]
P3[1]
P0[0]
P1[0]
P2[0]
P3[0]
P0[0]
P1[0]
P2[0]
P3[0]