CY7C63001A-SXC Cypress Semiconductor Corp, CY7C63001A-SXC Datasheet - Page 12

• Manufacturer Part Number: CY7C63001A-SXC
• Description: IC MCU 4K USB MCU LS 20SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001A-SXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1617

6.8.2
The General Purpose I/O interrupts are generated by signal
transitions at the Port 0 and Port 1 I/O pins. GPIO interrupts
are edge sensitive with programmable interrupt polarities.
Setting a bit HIGH in the Port Pull-up Register (see Figure 6-
11 and 6-12) selects a LOW to HIGH interrupt trigger for the
corresponding port pin. Setting a bit LOW activates a HIGH to
A block diagram of the GPIO interrupt logic is shown in Figure
6-19. The bit setting in the Port Pull-up Register selects the
interrupt polarity. If the selected signal polarity is detected on
the I/O pin, a HIGH signal is generated. If the Port Interrupt
Enable bit for this pin is HIGH and no other port pins are
requesting interrupts, the OR gate issues a LOW to HIGH
Note. If one port pin triggers an interrupt, no other port pin can
cause a GPIO interrupt until the port pin that triggered the
interrupt has returned to its inactive (non-trigger) state or until
its corresponding port interrupt enable bit is cleared (these
events ‘reset’ the clock of the GPIO Interrupt flip-flop, which
must be ‘reset’ to ‘0’ before another GPIO interrupt event can
‘clock’ the GPIO Interrupt flip-flop and produce an IRQ).
Note. If the port pin that triggered an interrupt is held in its
active (trigger) state while its corresponding port interrupt
Document #: 38-08026 Rev. *A
GPIO
Pin
IE0.7
IE1.7
b7
b7
W
W
0
0
1 = Enable
0 = Disable
GPIO Interrupt
Acknowledge
Interrupt
IE0.6
IE1.6
b6
b6
W
W
0
0
Port Interrupt
Enable Register
Figure 6-17. Port 0 Interrupt Enable Register (P0 IE – Address 0x04)
Figure 6-18. Port 1 Interrupt Enable Register (P1 IE – Address 0x05)
1 = Enable
0 = Disable
Port
Pull-Up
Register
IE0.5
IE1.5
Figure 6-19. GPIO Interrupt Logic Block Diagram
M
U
X
b5
b5
W
W
0
0
(Bit 6, Register 0x20)
GPIO Interrupt
1=L
0=H
Global
Enable
Æ
IE0.4
IE1.4
CLR
H
L
b4
b4
W
W
0
0
(1 input per
OR Gate
GPIO pin)
LOW interrupt trigger. Each GPIO interrupt is maskable on a
per-pin basis by a dedicated bit in the Port Interrupt Enable
Register. Writing a “1” enables the interrupt. Figure 6-17 and
Figure 6-18 illustrate the format of the Port Interrupt Enable
Registers for Port 0 and Port 1 located at I/O address 0x04 and
0x05 respectively. These write only registers are cleared
during reset, thus disabling all GPIO interrupts.
signal to clock the GPIO interrupt flip-flop. The output of the
flip-flop is further qualified by the Global GPIO Interrupt Enable
bit before it is processed by the Interrupt Priority Encoder. Both
the GPIO interrupt flip-flop and the Global GPIO Enable bit are
cleared by on-chip hardware during GPIO interrupt
acknowledge.
enable bit is cleared and then set, a GPIO interrupt event
occurs as the GPIO Interrupt flip-flop clock transitions from ‘1’
to ‘0’ and then back to ‘1’ (please refer to Figure 6-19). The
USB Controller does not assign interrupt priority to different
port pins and the Port Interrupt Enable Registers are not
cleared during the interrupt acknowledge process. When a
GPIO interrupt is serviced, the ISR must poll the ports to
determine which pin caused the interrupt.
IE0.3
IE1.3
b3
b3
W
W
0
0
I
GPIO Interrupt
Flip-Flop
D
CLR
IE0.2
IE1.2
b2
b2
W
W
0
0
Interrupt
Q
Encoder
Priority
IE0.1
IE1.1
b1
b1
W
W
0
0
CY7C63001A
CY7C63101A
Interrupt
IRQ
Vector
Page 12 of 25
IE0.0
IE1.0
b0
b0
W
W
0
0