PIC10F200-I/P Microchip Technology, PIC10F200-I/P Datasheet - Page 3

• Manufacturer Part Number: PIC10F200-I/P
• Description: IC PIC MCU FLASH 256X12 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F200-I/P

• Program Memory Type: FLASH
• Program Memory Size: 384B (256 x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 3
• Ram Size: 16 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC10F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 16 B
• Interface Type: USB
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162059 - HEADER INTRFC MPLAB ICD2 8/14PINAC164037 - MODULE SKT 6L PROMATE II SOT23
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
3.1
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising V
V
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
that all I/O are in the Reset state (high-impedance
inputs).
3.1.1
The programming sequence loads a word, programs,
verifies, and finally increments the PC.
Program/Verify mode entry will set the address to
0x1FF for the PIC10F200/204 and 0x3FF for the
PIC10F202/206. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
TABLE 3-1:
© 2007 Microchip Technology Inc.
Load Data for Program Memory
Read Data from Program Memory
Increment Address
Begin Programming
End Programming
Bulk Erase Program Memory
IL
ICSPCLK
ICSPDAT
to V
V
V
DD
DD
PP
COMMANDS AND
ALGORITHMS
Program/Verify Mode
. Then raise V
PROGRAMMING
Command
COMMAND MAPPING FOR PIC10F200/202/204/206
T
PPDP
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
PP
from V
T
HLD
0
IL
to V
IL
). This means
IHH
DD
. Once in
pin from
x
x
x
x
x
x
Preliminary
x
x
x
x
x
x
Mapping (MSb … LSb)
PIC10F200/202/204/206
0
0
0
1
1
1
3.1.2
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (T
and hold (T
of the clock (see Table 6-1).
Commands that do not have data associated with them
are required to wait a minimum of T
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait T
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output from
the PIC10F200/202/204/206, the ICSPDAT pin transi-
tions from the high-impedance input state to the low-
impedance output state at the rising edge of the second
data clock (first clock edge after the Start cycle). The
ICSPDAT pin returns to the high-impedance state at the
rising edge of the 16th data clock (first edge of the Stop
cycle). See Figure 3-3.
The commands that are available are described in
Table 3-1.
Note:
0
1
1
0
1
0
HLD
SERIAL PROGRAM/VERIFY
OPERATION
After every End Programming command,
a delay of T
1
0
1
0
1
0
1) times with respect to the falling edge
0
0
0
0
0
1
DIS
is required.
0, data (14), 0
0, data (14), 0
Externally Timed
Internally Timed
DS41228E-page 3
Data
DLY
2 measured
SET
DLY
1)
2