PIC10F222-I/MC Microchip Technology, PIC10F222-I/MC Datasheet - Page 3

• Manufacturer Part Number: PIC10F222-I/MC
• Description: IC PIC MCU FLASH 512X12 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F222-I/MC

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Core Processor: PIC
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 3
• Program Memory Type: FLASH
• Ram Size: 23 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC10
• No. Of I/o's: 4
• Ram Memory Size: 23Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Digital Ic Case Style: DFN
• Processor Series: PIC10F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 23 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 2 Channel
• Package: 8DFN EP
• Device Core: PIC
• Family Name: PIC10
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164334 - MODULE SOCKET FOR 8L 2X3MM DFNAC163020-2 - ADAPTER PROGRAM PIC10F 2X3 DFNAC162070 - HEADER INTRFC MPLAB ICD2 8/14P
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

3.0
3.1
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising V
V
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger inputs in
this mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
that all I/O are in the Reset state (high-impedance
inputs).
3.1.1
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x1FF for the PIC10F220 and 0x3FF for the
PIC10F222. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
3.1.2
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (T
and hold (T
of the clock (see Table 6-1).
© 2007 Microchip Technology Inc.
IL
ICSPCLK
ICSPDAT
to V
V
V
DD
DD
PP
COMMANDS AND
ALGORITHMS
Program/Verify Mode
. Then raise V
HLD
PROGRAMMING
SERIAL PROGRAM/VERIFY
OPERATION
1) times with respect to the falling edge
T
PPDP
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
PP
from V
T
HLD
0
IL
to V
IL
). This means
IHH
DD
. Once in
pin from
SET
1)
Commands that do not have data associated with them
are required to wait a minimum of T
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait T
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output
from the PIC10F22X, the ICSPDAT pin transitions from
the high-impedance input state to the low-impedance
output state at the rising edge of the second data clock
(first clock edge after the Start cycle). The ICSPDAT pin
returns to the high-impedance state at the rising edge
of the 16th data clock (first edge of the Stop cycle). See
Figure 3-4.
The commands that are available are described in
Table 3-1.
FIGURE 3-2:
Note:
ICSPCLK
ICSPDAT
V
V
DD
PP
After every End Programming command,
a delay of T
PIC10F220/222
PROGRAM/VERIFY MODE
EXIT
DIS
T
HLD
is required.
0
DS41266C-page 3
DLY
2, measured
DLY
2