MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 26

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NOTES:
1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
2. Example:
3. ACK is output and indicates the burst.
4. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
26
0–65535.
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst
on the internal XLB is executed. => LB = 1
Data bus width is 8 bit. => DS = 8
=> 4
Wait State is set to 10. => WS = 10
1 +
happens the bus can be driven within 4 IPB clocks by an other modules.
Sym
t
t
t
t
t
t
10
t
10
11
12
13
14
15
1
9
× 2 × (32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.
+ 32 = 43 => CS is asserted for 43 PCI cycles.
DATA hold after rising edge of PCI
ACK negation before CS negation
ACK assertion after CS assertion
CS assertion after TS assertion
DATA (rd)
DATA hold after CS negation
PCI CLK
ADDR
CS[x]
R/W
ACK
ACK pulse width
OE
TS
TS pulse width
Description
clock
t
t
2
6
Table 25. Burst Mode Timing (continued)
Figure 12. Timing Diagram—Burst Mode
t
14
MPC5200B Data Sheet, Rev. 4
t
4
4
t
LB
15
× 2 × (32/DS) × t
t
11
t
PCIck
Min
—
—
—
0
0
t
1
PCIck
4
LB
t
13
(WS + 1) × t
(DC + 1) × t
× 2 × (32/DS) × t
t
9
t
8
t
Max
PCIck
7.0
2.5
—
PCIck
PCIck
t
t
10
t
5
12
t
PCIck
t
7
3
Units Notes SpecID
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
(2),(3)
—
(4)
—
(3)
—
—
A7.32
A7.33
A7.34
A7.35
A7.36
A7.37
A7.38