MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 67

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote
computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations
of the MPC5200B.
3.4.2
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
3.4.2.1
The MPC5200B functional pin interface and internal logic provides access to the embedded e300 processor core through the
Freescale (formerly Motorola) standard COP/BDM interface.
shown reflects only the COP/BDM connector order.
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset
the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.
Freescale Semiconductor
e300 COP/BDM Interface
1
2
3
4
Boards Interfacing the JTAG Port via a COP Connector
Pin #
BDM
With respect to the emulator tool’s perspective, Input is really an output from the embedded
output is really an input to the core.
From the board under test, power sense for chip power.
HALTED is not available from e300 core.
Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5200B
internally ties CORE_QACK to GND in its normal/functional mode (always asserted).
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TEST_SEL_0
JTAG_TRST
MPC5200B
JTAG_TMS
JTAG_TDO
JTAG_TCK
JTAG_TDI
HRESET
SRESET
I/O Pin
—
—
—
—
—
—
—
—
Table 53. COP/BDM Interface Signals
MPC5200B Data Sheet, Rev. 4
Connector
ckstp_out
halted
hreset
sreset
VDD
qack
BDM
GND
GND
KEY
N/C
N/C
tms
trst
tdo
tck
tdi
2
4
3
Table 53
Pull Up/Down
100k Pull-Up
100k Pull-Up
100k Pull-Up
100k Pull-Up
Internal
—
—
—
—
—
—
—
—
—
—
—
—
gives the COP/BDM interface signals. The pin order
Pull Up/Down
10k Pull-Up
10k Pull-Up
10k Pull-Up
10k Pull-Up
10k Pull-Up
10k Pull-Up
External
—
—
—
—
—
—
—
—
—
—
e300
core and
I/O
—
—
—
—
—
—
O
O
O
O
O
O
O
I
I
I
1
67