MPC8555EVTAPF Freescale Semiconductor, MPC8555EVTAPF Datasheet - Page 50

• Manufacturer Part Number: MPC8555EVTAPF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555EVTAPF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Not applicable / RoHS Compliant
• Features: -

JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8555E.
Table 38
At recommended operating conditions (see
50
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure
(reference)(state)
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
t
the time data input signals (D) went invalid (X) relative to the t
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
JTG
clock reference (K) going to the high (H) state or setup time. Also, t
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
32). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
provides the JTAG AC timing specifications as defined in
for inputs and t
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK)
Parameter
(first two letters of functional block)(reference)(state)(signal)(state)
Table
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
2).
TCLK
TCLK
TMS, TDI
TMS, TDI
.
.
TDO
TDO
TDO
JTG
t
JTGR
Symbol
t
t
t
t
t
t
t
t
t
t
t
JTDXKH
JTKHKL
JTDVKH
JTKLOV
JTKLDX
JTKLOX
JTKLDZ
JTKLOZ
JTKLDV
JTIVKH
JTIXKH
clock reference (K) going to the high (H) state. Note that,
t
t
f
TRST
JTG
JTG
& t
JTGF
(first two letters of functional block)(signal)(state)
JTDXKH
2
Figure 33
symbolizes JTAG timing (JT) with respect to
TCLK
Min
30
15
25
20
25
—
—
0
0
4
0
4
4
3
3
for outputs. For example, t
to the midpoint of the signal in
through
Max
33.3
20
25
19
—
—
—
—
—
—
—
—
—
2
9
Freescale Semiconductor
1
Figure
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
JTDVKH
36.
Notes
5, 6
3
4
4
5
5