MPC8555EVTAPF Freescale Semiconductor, MPC8555EVTAPF Datasheet

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... PowerQUICC™ III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document refer to http://www.freescale.com or contact your Freescale sales office. © Freescale Semiconductor, Inc., 2008. All rights reserved. MPC8555EEC Rev. 4.2, 1/2008 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8 3 ...

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... Interrupt Controller Figure 1. MPC8555E Block Diagram Figure 1 shows the 256-Kbyte L2 Cache/ SRAM e500 Core 32-Kbyte L1 32-Kbyte L1 I Cache D Cache Core Complex Bus 64/32b PCI Controller 0/32b PCI Controller DMA Controller 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs 10/100/1000 MAC Freescale Semiconductor ...

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... Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller — Handles serial protocols and virtual DMA MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 3 ...

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... General-purpose parallel ports—16 parallel I/O lines with interrupt capability • 256 Kbytes of on-chip memory — Can act as a 256-Kbyte level-2 cache — Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 4 Freescale Semiconductor ...

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... Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 5 ...

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... Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers — Support for Ethernet physical interfaces: – 10/100/1000 Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 addressing mode 2 C interface Freescale Semiconductor ...

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... Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 7 ...

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... I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 8 Freescale Semiconductor ...

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... The MPC8555Erequires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up DDn (I/O supplies MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol ...

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... Recommended Value V 1.2 V ± 1.3 V± (for 1 GHz only) AV 1.2 V ± 1.3 V ± (for 1 GHz only) GV 2.5 V ± 125 3.3 V ± 165 mV DD 2.5 V ± 125 mV OV 3.3 V ± 165 GND GND to GV REF LV GND GND and Unit ° 105 Freescale Semiconductor ...

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... LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied appropriate for the SSTL2 electrical signaling standard. DD MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor + 20 GND Not to Exceed 10% ...

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... The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 (Min) +7 (Max (Max) 62.5 ns +3.6 V –3.5 V Table 3. Output Drive Capability Programmable Output Impedance (Ω (default (default 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) Supply Notes Voltage 2.5/3 3 Freescale Semiconductor ...

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... Maximum power is based on a nominal voltage artificial smoke test. 6. The nominal recommended V = 1.3V for this speed grade. DD Notes MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor (1) (2) Table 4. Power Dissipation V Typical Power DD 400 1.2 500 1.2 600 1.2 533 1 ...

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... Unit Comments W — W — W — W — W — W — W Multiply using two 32b ports W W — W — W — W — W — W Multiply by number of interfaces used — W — W — W — W — W — W — W — W — TDM channels, multiply by number of TDM channels. Freescale Semiconductor ...

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... EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 6. SYSCLK AC Timing Specifications Symbol ...

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... Table 10. PLL and DLL Lock Times Min — 7680 Typical Max Unit Notes — — ns — — ns Max Unit Notes μs — — SYSCLKs μs — — SYSCLKs — SYSCLKs 5 SYSCLKs Max Unit Notes μs 100 122,880 CCB Clocks Freescale Semiconductor — — — 1 — — ...

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... Output leakage is measured with all outputs disabled Table 12 provides the DDR capacitance. Parameter/Condition Input/output capacitance: DQ, DQS, MSYNC_IN Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Symbol Min GV 2.375 DD 0.49 × REF V ...

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... MHz 2.0 266 MHz 2.65 200 MHz 3.8 t DDKHCS 333 MHz 2.8 266 MHz 3.45 200 MHz 4.6 Max Unit Notes MV – 0.31 V — REF GV + 0.3 V — 750 1125 Max Unit Notes 200 300 400 — — — Freescale Semiconductor ...

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... The data strobe should be centered inside of the data eye at the pins of the MPC8555E. 7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8555E. Note that t conventions described in note 1. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 2.5 V ± 5 ...

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... Figure 5. DDR SDRAM Output Timing Diagram for Source Synchronous Mode MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 20 MCK[n] MCK[n] t MCK t AOSKEWmax) CMD t AOSKEW(min) CMD NOOP AOSKEW t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMH t DDKHDS t DDKLDS DDKLDX t DDKHDX NOOP Measurement t DDKLME Freescale Semiconductor ...

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... Low-level input voltage Input current High-level output voltage Low-level output voltage Note: 1. Note that the symbol this case, represents the OV IN MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor = 50 Ω Figure 6. DDR AC Test Load DDR Unit MV ± ...

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... Value f / 1048576 CCB_CLK CCB_CLK 16 th sampled 0 after the 1-to-0 transition of the start th sample. Characteristics.” 19. The potential applied to the input of a GMII, MII, TBI, RGMII, or into a GMII receiver powered from a 2.5-V supply). Tolerance OH Unit Notes baud 3 baud 1, 3 — Freescale Semiconductor ...

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... Input low voltage (LV = Min Input high current ( Input low current (V = GND) IN Note: 1. Note that the symbol this case, represents the LV IN MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Conditions — –4 Min 4 Min OL DD — — — ...

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... GTX t t GTXH GTXF t GTKHDX t GTKHDV Figure 7. GMII Transmit AC Timing Diagram Min Typ Max — 8.0 — 40 — 60 2.5 — — 0.5 — 5.0 2,4 — — 1.0 symbolizes GMII GTKHDV symbolizes GMII transmit timing (GT) with respect t GTXR Freescale Semiconductor Unit ...

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... Guaranteed by design. Figure 8 provides the AC test load for TSEC. Output Figure 9 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol t GRX t /t GRXH GRX ...

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... MII(M) transmit (TX) clock. For rise and fall MTX t MTX t t MTXH MTXF t MTKHDX Figure 10. MII Transmit AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 for outputs. For example, t MTKHDX t MTXR Freescale Semiconductor Unit ...

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... Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 11 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol 2 t MRX t MRX ...

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... Min Typ Max — 8.0 — 40 — 60 2.0 — — 1.0 — — — — 1.0 (first two letters of functional block)(signal)(state for outputs. For example, t (K) going high (H) until the referenced data t TTXR t TTXR t TTKHDX Freescale Semiconductor Unit TTKHDV ...

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... R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. Figure 13 shows the TBI receive AC timing diagram. RX_CLK1 RXD[9:0] RX_CLK0 MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol t TRX t SKTRX ...

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... SKRGT 6 t RGT RGTH RGT RGTH RGT 6,7 6 RGTR , RGTF represents the TBI (T) receive (RX) clock. Note also that the RGT Min Typ Max –500 0 500 1.0 — 2.8 7.2 8.0 8 — — 0.75 of the lowest speed RGT Freescale Semiconductor Unit ...

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... Table 27. MII Management DC Electrical Characteristics Parameter Symbol Supply voltage (3 Output high voltage V Output low voltage V Input high voltage V Input low voltage V MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t ...

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... Max — 40 –600 — Table 1 and Table 2. Max Unit — 10.4 MHz — 1120 ns — — ns 2*[1/(f /8)] ns ccb_clk — 2*[1/(f /8)] ns ccb_clk — — ns — — ns — — for outputs. For example, t Freescale Semiconductor Unit μA μA Notes MDKHDX ...

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... High-level input voltage Low-level input voltage Input current High-level output voltage Low-level output voltage Note: 1. Note that the symbol this case, represents the OV IN MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t MDC t t MDCF MDCH t MDDVKH t ...

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... LBKHOX2 LWE[0: (default) LWE[0: LBKHOZ1 LWE[0: (default) Min Max Unit Notes 6.0 — — 150 1.8 — 1.7 — 0.5 — 1.0 — 1.5 — — 2 3.8 — 2 4.0 — 2 4.1 0.7 — 1.6 0.7 — 1.6 — 2 4.2 Freescale Semiconductor ...

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... LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 7 Configuration Symbol LWE[0: ...

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... Figure 16. Local Bus C Test Load 1 Min Max Unit — 0.8 ns 2.3 –2.7 — ns –1.8 –2.7 — ns –1.8 — 1.0 ns 2.4 — 1.0 ns 2.4 symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for Ω Freescale Semiconductor Notes the signal ...

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... LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBIVKH1 t LBIVKH1 t LBKHOZ1 t t LBKHOV1 ...

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... Output (Address) Signal: LAD[0:31] LALE Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHKT t LBIVKH1 t LBIVKH2 t LBKLOV1 t t LBKLOV2 t t LBKLOV3 t LBOTOT t LBIXKH1 t LBIXKH2 t LBKLOZ1 LBKLOX1 t LBKLOZ2 LBKLOX2 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...

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... Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHKT t t LBKLOX1 LBKLOV1 t LBIVKH2 t LBIVKH1 t LBKLOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...

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... Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHKT t t LBKLOX1 LBKLOV1 t LBIVKH2 t LBIVKH1 t LBKLOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... SCC/SMC/SPI inputs—internal clock (NMSI) input hold time SCC/SMC/SPI inputs—external clock (NMSI) input setup time SCC/SMC/SPI inputs—external clock (NMSI) input hold time TDM inputs/SI—input setup time MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 32. CPM DC Electrical Characteristics Symbol Condition V ...

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... PIIXKH t 1.5 FCCH for outputs. For example, t FIIVKH symbolizes the TDM timing TDIXKH (K) going to FCC 1 2 Symbol Min Max t 1 5.5 FIKHOX FEKHOX t 0.5 10 NIKHOX NEKHOX t 2.5 11 TDKHOX PIKHOX symbolizes the FCC FIKHOX Ω Freescale Semiconductor Unit CLK Unit for ...

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... GFMR TCI = 1) Figure 25. FCC External AC Timing Clock Diagram Figure 26 shows Ethernet collision timing on FCCs. COL (Input) Figure 26. Ethernet Collision AC Timing Diagram (FCC) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 33 and t FIIXKH t FIIVKH t FIKHOX ...

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... SPI AC timings are internal mode when it is master because SPICLK is an output, and external mode when it is slave. 2 SPI AC timings refer always to SPICLK MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 NEIXKH t NEKHOX t NIIXKH t NIIVKH t NIKHOX NOTE . Freescale Semiconductor ...

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... High period of SCL 2 Start condition setup time 2 Start condition hold time 2 Data hold time 2 Data setup time SDA/SCL rise time MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t TDIXKH t TDIVKH t TDKHOX Figure 29. TDM Signal AC Timing Diagram t PIIXKH PIIVKH Figure 30 ...

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... MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 48 Table 35. I2C Timing (continued) Expression Min t - SFALL t 2/(divider * f SCHDH *prescaler)=2*(I2BRG[DIV]+3) SCL *prescaler) SCL t SCHCL t SCLDX t t SRISE SFALL Figure 31. CPM I2C Bus Timing Diagram All Frequencies Max 1/( SCL ) - SCL t SDVCH t SCHDH Freescale Semiconductor Unit s s ...

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... Start condition hold time Data hold time Data setup time SDA/SCL rise time SDA/SCL fall time Stop condition setup time MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 36. CPM I2C Timing (f =100 kHz) SCL Expression f SCL ...

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... JTG . TCLK . TCLK Figure 33 through Figure 36. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 0 — — 25 — — — — — the midpoint of the signal in TCLK for outputs. For example, t JTDVKH symbolizes JTAG timing (JT) with respect to Freescale Semiconductor ...

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... JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (OV DD /2) VM ...

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... C DC Electrical Characteristics of 3.3 V ± 5%. DD Symbol 0.7 × 0.1 × I2KLKV t I2KHKL switched off JTIXKH Input Data Valid Output Data Valid 2 C interface of the MPC8555E. Min Max Unit 0.3 × OV –0 0.2 × 250 μA –10 10 — Freescale Semiconductor Notes ...

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... LOW period (t I2DVKH capacitance of one bus line in pF Guaranteed by design. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 2 C interface of the MPC8555E. 2 Table 40 Electrical Specifications Table 39) ...

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... Test Condition ≥ (min OUT OH ≤ (max) IL OUT min –100 μ min 100 μ symbol referenced Ω I2KHKL I2CF t I2CR t I2PVKH P 1 Min Max 0.3 DD –0.3 0.8 — ±5 OV – 0.2 — DD — 0.2 Table 1 and Table 2. Freescale Semiconductor S Unit V V μ ...

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... The reset assertion timing requirement for HRESET is 100 μs. 9. Guaranteed by characterization. 10.Guaranteed by design. Figure 16 provides the AC test load for PCI. Output MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 42 provides the PCI AC timing specifications at 66 NOTE NOTE 1 Symbol ...

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... Pitch Minimum module height 3.07 mm Maximum module height 3.75 mm Solder Balls Ball diameter (typical) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 PCIVKH CLK t PCKHOV t PCKHOZ Output 8.7 mm × 9.3 mm × 0. × 783 Sn/36 Pb PCIXKH Freescale Semiconductor ...

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... Capacitors may not be present on all devices. 6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. The socket lid must always be oriented to A1. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package and Pin Listings 57 ...

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... AF5 AF3, AE4, AG4, AE5 AE6 AG5, AH5, AF6, AG6 AH25 AH27 AC18 Power Pin Type Notes Supply I/O OV — DD I/O OV — — I/O OV — — DD I/O OV — — — DD I/O OV — DD Freescale Semiconductor ...

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... MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MSYNC_IN MSYNC_OUT LA[27] MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number AD18, AE18, AE19, AD19 AC22 AD20 AC20 AD21 AE21, AD22, AE22, AC23 AE20 AC21 AC19 ...

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... V28 V27 V23 V22 T27 T28 AB28, AB27 T23, P24 DMA H5, G4 H6, G5 H7, G6 Programmable Interrupt Controller AG17 AG16 Power Pin Type Notes Supply I/O OV — — — — I/O OV — I — — — — — — — DD Freescale Semiconductor ...

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... TSEC1_RX_ER TSEC1_RX_CLK Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_TXD[7:4] TSEC2_TXD[3:0] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number AB20 Y20 AF26 AH24 AB21 Ethernet Management Interface F1 E1 Gigabit Reference Clock ...

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... AH23 System Control AH16 AG20 AF20 M11 G1 Debug N12 G2 J9 Clock AH21 AB23 AF22 Power Pin Type Notes Supply I LV — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

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... THERM0 THERM1 ASLEEP MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number JTAG AF21 AG21 AF19 AF23 AG23 DFT AG19 AB22 AG22 AH20 AG26 Thermal Management AG2 AH3 Power Management AG18 Power and Ground Signals ...

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... Reference LV — DD Voltage; Three-Speed Ethernet I/O (2.5 V, 3.3 V) Reference MV — REF Voltage Signal; DDR — — 16 PCI, 10/100 OV — DD Ethernet, and other Standard (3.3 V) — — 15 Power for Core (1.2 V) — — 13 Power for Core V — DD (1.2 V) I/0 OV — DD Freescale Semiconductor ...

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... If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin. 22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number R7 W6, W7, W8 AC3, AC2, AC1, AD6, AE3, AE2 Ratio.” ...

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... MHz Min 100 Ratio,” for ratio settings. Table 44 provides the clocking 833 MHz 1000 MHz Unit Notes Max Min Max 833 400 1000 MHz Ratio,” for ratio settings. Unit Notes Max 166 MHz Section 15.2, “Platform/System PLL Freescale Semiconductor ...

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... There is no default for this PLL ratio; these signals must be pulled to the desired values. For specifications on the PCI_CLK, refer to the PCI 2.2 Specification. Binary Value of LA[28:31] Signals MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 46. Table 46. CCB Clock Ratio Ratio Description ...

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... SYSCLK (MHz Platform/CCB Frequency (MHz) 200 267 208 333 200 250 200 267 333 225 300 250 333 300 Table 47. 83 100 111 133 200 222 267 250 300 333 333 Freescale Semiconductor ...

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... This spring force should not exceed 10 pounds force. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 49. Package Thermal Characteristics Figure 43. The heat sink should be attached to the printed-circuit ...

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... Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 70 FC-PBGA Package Heat Sink Heat Sink Clip Lid Die Printed-Circuit Board 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 Freescale Semiconductor ...

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... Substrate and Solder Balls (25 × 25 × 1.6 mm MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Unit W/(m × K) 360 360 z 360 Side View of Model (Not to Scale) x 4.4 1.2 y Top View of Model (Not to Scale) Figure 44 ...

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... If the support fixture around the package prevents sliding off the heat sink, MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 72 Table 49, the intrinsic internal conduction thermal resistance paths Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Radiation Convection Freescale Semiconductor ...

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... Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease ...

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... INT JC is obtained 30°C + 5°C + (0.96°C/W + θ versus airflow velocity for a Thermalloy heat sink SA of about 3.3°C/W, thus SA+ Table 5. ) may be in the range of 5° may be about 1°C/W. For the INT = 0.96, and a power consumption (P ) × 8 Freescale Semiconductor ) ...

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... For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 0 ...

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... Figure 48 and provide exploded views of the plastic fence, heat sink, and spring clip. Figure 48. Exploded Views ( Heat Sink Attachment using a Plastic Fence MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 76 Freescale Semiconductor ...

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... For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Thermal 77 ...

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... The ) DD Section 15.3, “e500 Core PLL 5 respectively). The AV level should always be equivalent through a low frequency filter scheme such DD Figure 50, one to each of the five AV Ratio.” Ratio.” DD pins pin being supplied to minimize DD Freescale Semiconductor ...

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... GND. Then, the value of each resistor is varied until the pad voltage is OV output impedance is the average of two components, the resistances of the pull-up and pull-down devices. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 10 Ω 2.2 µF 2.2 µ ...

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... Table 50. Impedance Characteristics Management 43 Target 43 Target NA Table 105°C. j and R are designed to be close to each SW2 SW1 . Second, the output voltage is measured . The term source PCI DDR DRAM Symbol Unit 25 Target 20 Target 25 Target 20 Target Freescale Semiconductor = R term , DD Ω Ω Ω DIFF ...

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... TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor System Design Information 81 ...

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... MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 82 allows the COP port to independently assert HRESET or TRST, Figure 52, for connection to the target system, and is 2 COP_TDO COP_TDI 3 4 COP_TRST COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Figure 52. COP Connector Physical Pinout Figure 52 is common to Freescale Semiconductor ...

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... Tie TCK to OV through a 10 kΩ resistor. This prevents TCK from changing state and reading DD incorrect data into the device. • No connection is required for TDI, TMS, or TDO. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor System Design Information 83 ...

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... COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK 10 kΩ Figure 53. JTAG Interface Connection kΩ 6 SRESET 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK Freescale Semiconductor ...

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... Table 0 6/2005 Initial release. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 51. Document Revision History Substantive Change(s) Figure 3, ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.” Section 2.1.2, “Power Sequencing.” Section 2.1.2, “Power Sequencing.” ...

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... Table 52. Part Numbering Nomenclature pp t Temperature 2 Package 1 Range PX = FC-PBGA VT = FC-PBGA (lead free) Listings,” for more information on available package types Processor Platform 3 Frequency Frequency AJ = 533 MHz D = 266 MHz AK = 600 MHz E = 300 MHz AL = 667 MHz F = 333 MHz AP = 833 MHz AQ = 1000 MHZ Freescale Semiconductor r Revision 4 Level ...

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... CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 54. Part Marking for FC-PBGA Device MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Figure 54. MPC85nn ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...