MC68LC040RC25A Freescale Semiconductor, MC68LC040RC25A Datasheet - Page 213

IC MPU 32BIT 25MHZ 179-PGA

MC68LC040RC25A

Manufacturer Part Number
MC68LC040RC25A
Description
IC MPU 32BIT 25MHZ 179-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68LC040RC25A

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Part Number:
MC68LC040RC25A
Manufacturer:
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Quantity:
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Case 1
Case 2
MOTOROLA
If DLE is negated and meets setup time specification #35 to the rising edge of BCLK
when the bus read is terminated, latch A is transparent, and the read data must meet
setup and hold time specifications #36 and #37 to the rising edge of BCLK. Read timing
is similar to normal timing for this case.
If DLE is asserted, the data bus levels are latched and held internally. D31–D0 must
meet setup and hold time specifications #32 and #33 to the falling edge of DLE, and can
transition to a new level once DLE is asserted. D31–D0 must still meet setup time
specification #36 to BCLK, but not hold time specification #37, since the data is
internally held valid as long as DLE remains asserted low.
D0–D31 IN
(READ)
BCLK
DLE
TA
Figure 7-48. DLE versus Normal Data Read Timing
Freescale Semiconductor, Inc.
36
For More Information On This Product,
35
D0–D31 IN
CASE 1
(READ)
BCLK
Go to: www.freescale.com
M68040 USER’S MANUAL
TA
37
DLE MODE DATA BUS TIMING
NORMAL DATA BUS TIMING
15
32
16
31
CASE 2
36
33
34
7- 71

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