MC68LC040RC25A Freescale Semiconductor, MC68LC040RC25A Datasheet - Page 377

• Manufacturer Part Number: MC68LC040RC25A
• Description: IC MPU 32BIT 25MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC040RC25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

APPENDIX B
MC68EC040
The MC68EC040 is Motorola's third generation of M68000-compatible, high-performance,
32-bit microprocessors. The MC68EC040 is an embedded controller employing a highly
integrated architecture to provide very high performance in a monolithic HCMOS device. The
MC68EC040 integrates an MC68040-compatible integer unit, an access control unit (ACU),
and independent 4-Kbyte instruction and data caches. A six-stage instruction pipeline, mul-
tiple internal buses, and a full internal Harvard architecture, including separate caches for
both instruction and data accesses, provides a high degree of instruction execution parallel-
ism. The inclusion of on-chip bus snooping logic, which directly supports cache coherency
in multimaster applications, enhances cache functionality.
The MC68EC040 is user-object-code compatible with previous members of the M68000
family and is specifically optimized to reduce the execution time of compiler-generated code.
The MC68EC040 is pin compatible with the MC68040 and MC68LC040. The MC68EC040
is implemented in Motorola's latest HCMOS technology, providing an ideal balance between
speed, power, and physical device size. Figure B-1 provides a simplified block diagram of
the MC68EC040.
The main features of the MC68EC040 include:
MOTOROLA
• MC68040-Compatible Integer Execution Unit
• 4-Kbyte Instruction Cache and 4-Kbyte Data Cache Accessible Simultaneously
• 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Bursting
• User-Object-Code Compatible with All M68000 Microprocessors
• Concurrent Integer Unit, ACU, and Bus Controller Operation Maximizes Throughput
• Low-Latency Bus Accesses for Reduced Cache-Miss Penalty
• Multimaster/Multiprocessor Support via Bus Snooping
• 4-Gbyte Direct Addressing Range
Interface
Rev. 2.3 contains timing informationg for 40 MHz operation.
Refer to chang bars for these additions.
All references to MC68EC040 also apply to the MC68EC040V.
Refer to Appendix C MC68040V and MC68EC040V for more
information on the MC68EC040V.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
NOTE
REV2.3 (01/31/2000)
B-1