XS1-G02B-FB144-C4 XMOS, XS1-G02B-FB144-C4 Datasheet - Page 2
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XS1-G02B-FB144-C4
Manufacturer Part Number
XS1-G02B-FB144-C4
Description
IC MPU 32BIT DUAL CORE 144FBGA
Manufacturer
XMOS
Datasheet
1.XS1-G02B-FB144-C4.pdf
(22 pages)
Specifications of XS1-G02B-FB144-C4
Processor Type
XCore 32-Bit
Speed
800MIPS
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
144-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1006
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XS1-G2 144BGA Datasheet (2.6)
wide range of applications and systems.
with external components and channels for com-
A high performance switch supports low latency
XS1-G2 Package Features
XCore Resources (per core)
Description
The XS1-G family blends a powerful pro-
grammable fabric based on multi-threaded pro-
cessors with a high-level programming language
design flow. XMOS chips are general-purpose
programmable devices that can be used in a
The XS1-G2 device integrates two XCore™ de-
vices. Each XCore contains a 32-bit processor,
SRAM memory, I/O ports for communicating
municating with other devices.
OTP memory is provided for application boot
code and security keys, with a secure mode that
disables debug and prevents read-back of mem-
ory contents.
and deterministic communication between the
threads in different XCores.
The XMOS architecture is unique in its direct sup-
port for concurrent processing (multi-threading),
event handling, communication and timed I/O
operations.
Two XCores providing 800MIPS and up to 16 concurrent, deterministic real-time tasks
88 user I/O pins, dynamically configurable as input, output or bi-directional
4 XMOS Links
Threads
Channel Ends
Timers
Clock Blocks
Thread Synchronisers
Hardware Locks
SRAM
OTP Memory
8
32
10
6 (includes the reference clock)
7
4
64KBytes
8KBytes
www.xmos.com
I/O
1 x 32bit
2 x 16bit
16 x 1bit
8KBytes
Output
4 x 8bit
6 x 4bit
Input/
Ports
JTAG
XS1-G2
XCore0
OTP
TAP
7 Synchronisers
Links
Links
10 Timers
8 Threads per XCore
Constant Pointer
Stack Pointer
Link Register
Processor
Data Pointer
Per Thread
Reg 10
Reg 11
Reg 0
Reg 1
Reg 2
Reg 3
Reg 4
Reg 5
Reg 6
Reg 7
Reg 8
Reg 9
XCore
Switch
JTAG
64KBytes SRAM
PLL
Ctrl
JTAG Debug
6 Clock Blocks
4 Locks
XCore2
Channel
Ends
(32)
2/22
I/O