XS1-L02A-QF124-C5 XMOS, XS1-L02A-QF124-C5 Datasheet - Page 11

• Manufacturer Part Number: XS1-L02A-QF124-C5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-C5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1020

XS1-L2 124QFN Datasheet (1.5)
The XS1-L2 device contains a standard 5 pin JTAG interface, which allows the following
The JTAG interface on the XS1-L2 consists of the following signals:
The TRST_N pin must be driven low for at least 100ns after the power supplies are
The XS1-L2 JTAG structure is conceptually composed of two XS1-L1 JTAG structures
The boundary scan TAP is a standard 1149.1 compliant TAP and can be used for
3.5 One Time Programmable Memory
Functional description
OTP_VDDIO OTP Power Supply. Must be 3V3. This supply must be at its nominal
3.6 JTAG Operation
functionality:
stable to reset the JTAG circuitry. If JTAG debug is not required, the TRST_N pin can
be tied low to hold the JTAG port in reset.
connected together. The XS1-L2 device can therefore be looked at externally as two
L1 devices connected in a chain as shown in the JTAG chain structure diagram.
Each XS1-L1 structure contains multiple TAP controllers, each enabling different
functionality. For the XS1-L1, directly after reset, two TAP controllers are present in
the JTAG chain - the boundary scan TAP (BS TAP) and the chip TAP (CHIP TAP). This
means for the L2 there will be four TAP controllers present in total.
boundary scan of the I/O pins of the device. The chip TAP allows access into the
Signal
OTP_VDDIO
Signal
TCK
TMS
TRST_N
TDI
TDO
level before the core supply is enabled.
Boundary scan testing for verifying printed circuit board connectivity.
In-circuit source level debugging of the XCores.
Programming of the One Time Programmable (OTP) ROM.
Pin ID
B32
Pin ID
B10
B11
B13
B12
B9
I/O
I, PU, ST
I, PU, ST
I, PU, ST
I, PU, ST
OT, PD
www.xmos.com
I/O
pwr
Description
OTP Power Supply
Description
Test clock
Test mode select
Test reset (active low)
Test data in
Test data out
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