MPC8360VVAGDGA Freescale Semiconductor, MPC8360VVAGDGA Datasheet - Page 33

• Manufacturer Part Number: MPC8360VVAGDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8360VVAGDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 13
Figure 14
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock fall time, (80% to 20%)
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
provides the AC test load.
shows the MII receive AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
RXD[3:0]
RX_CLK
RX_DV
RX_ER
Parameter/Condition
Output
Table 30. MII Receive AC Timing Specifications (continued)
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Figure 14. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
DD
/OV
MRX
t
DD
MRX
Z
clock reference (K) going to the low (L) state or hold time. Note that, in general,
Figure 13. AC Test Load
MRDXKL
of 3.3 V ± 10%.
0
= 50 Ω
Valid Data
symbolizes MII receive timing (GR) with respect to the time data input
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
t
MRXF
(first two letters of functional block)(signal)(state)(reference)(state)
Symbol
for outputs. For example, t
t
MRXF
1
R
t
MRDXKH
t
L
MRXR
= 50 Ω
Min
1.0
LV
DD
MRDVKH
/2
Typ
—
MRX
symbolizes MII receive
clock reference (K)
Max
4.0
Unit
for
ns
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