MPC8360VVAGDGA Freescale Semiconductor, MPC8360VVAGDGA Datasheet - Page 92
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MPC8360VVAGDGA
Manufacturer Part Number
MPC8360VVAGDGA
Description
IC MPU POWERQUICC II PRO 740TBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8360CZUAJDG.pdf
(108 pages)
Specifications of MPC8360VVAGDGA
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
740-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8360E-RDK
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
For Use With
MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8360VVAGDGA
Manufacturer:
AVX
Quantity:
3 000
Company:
Part Number:
MPC8360VVAGDGA
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC8360VVAGDGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clocking
22.3
The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and
RCWL[CEVCOD] parameters.
block PLL.
92
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
QUICC Engine Block PLL Configuration
Core VCO frequency = Core frequency × VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO
frequency is in the range of 800–1800 MHz. Having a core frequency below
the CSB frequency is not a possible option because the core frequency must
be equal to or greater than the CSB frequency.
RCWL[CEPMF] RCWL[CEPDF]
0–1
11
00
01
10
11
00
01
10
11
00
01
10
11
Table 74. QUICC Engine Block PLL Multiplication Factors
00000
00001
00010
00011
00100
RCWL[COREPLL]
Table 73. e300 Core PLL Configuration (continued)
Table 74
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
2–5
shows the multiplication factor encodings for the QUICC Engine
0
0
0
0
0
6
1
0
0
0
0
1
1
1
1
0
0
0
0
NOTE
Multiplication Factor = RCWL[CEPMF]/
core_clk : csb_clk
Ratio
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
(1 + RCWL[CEPDF])
QUICC Engine PLL
Reserved
× 16
× 2
× 3
× 4
VCO divider
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
8
2
4
8
8
2
4
8
8
2
4
8
8
Freescale Semiconductor