EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 115
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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Part Number
Manufacturer
Quantity
Price
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PS006614-1208
I
Table 49. I
I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
2
2
C Slave Address Register
C Extended Slave Address Register
The I2Cx_SAR register, indicated in
SLAVE mode and allows 10-bit addressing in conjunction with the I2Cx_xSAR register.
I2Cx_SAR[7:1] = SLA[6:0] is the 7-bit address of the I
When the I
I2Cx_SAR[7] corresponds to the first bit received from the I
When the register receives an address starting with
11110b
I
interrupt at this point). After the next byte of the address (I2Cx_xSAR) is received, the I
generates an interrupt and enters SLAVE mode. Then I2Cx_SAR[2:1] is used as the upper
2 bits of the 10-bit extended address. The full 10-bit address is returned by
{I2Cx_SAR[2:1], I2Cx_xSAR[7:0]}.
The I2Cx_xSAR register, listed in
register to provide 10-bit addressing for the I
value forms the lower 8 bits of the 10-bit slave address. The full 10-bit address is returned
by {I2Cx_SAR[2:1], I2Cx_xSAR[7:0]}.
When the register receives an address starting with
11110b
I
interrupt at this point). After the next byte of the address (I2Cx_xSAR) is received, the I
generates an interrupt and enters SLAVE mode. Then I2Cx_SAR[2:1] is used as the upper
2 bits of the 10-bit extended address. The full 10-bit address is returned by
{I2Cx_SAR[2:1], I2Cx_xSAR[7:0]}.
2
2
C sends an ACK after receiving the I2Cx_SAR byte (the device does not generate an
C sends an ACK after receiving the I2Cx_SAR byte (the device does not generate an
2
C Slave Address Registers
), the I
), the I
Value Description
00h–
7Fh
0
1
2
C receives this address after a START condition, it enters SLAVE mode.
2
2
C recognizes that a 10-bit slave addressing mode is being selected. The
C recognizes that a 10-bit slave addressing mode is being selected. The
The 7-bit slave address, or the lower 7 bits of the slave address,
when operating in 10-bit mode.
The I
The I
R/W
7
0
2
2
C is not enabled to recognize the General Call Address.
C is enabled to recognize the General Call Address.
R/W
6
0
R/W
Table
5
0
Table
50, is used in conjunction with the I2Cx_SAR
(I2C0_SAR = C8h, I2C1_SAR = D8h)
R/W
49, lists the 7-bit address of the I
4
0
2
C when in SLAVE mode. The I2Cx_SAR
R/W
F7h
F7h
3
0
2
to
to
C when in 7-bit SLAVE mode.
F0h
F0h
R/W
2
2
0
C bus.
(I2Cx_SAR[7:3] =
(I2Cx_SAR[7:3] =
Product Specification
R/W
1
0
I2C Serial I/O Interface
R/W
2
C when in
0
0
2
2
C
C
105
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