EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 154

IC WEBSERVER 50MHZ XTEMP 100lQFP

EZ80190AZ050EC

Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80190AZ050EC

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123

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Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80190AZ050EC
Manufacturer:
Zilog
Quantity:
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Part Number:
EZ80190AZ050EC00TR
Manufacturer:
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Quantity:
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PS006614-1208
DMA Destination Address Registers
Table 78. DMA Destination Address Registers DMA0_DAR_L = F1h, DMA0_DAR_H = F2h,
DMA Byte Count Registers
Bit
Position
[7:0]
DMAx_SAR_L,
DMAx_SAR_H,
or
DMAx_SAR_U
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Bit
Position
[7:0]
DMAX_DAR_L,
DMAX_DAR_H,
or
DMAX_DAR_U
DMA0_DAR_U = F3h, DMA1_DAR_L = FAh, DMA1_DAR_H = FBh, DMA1_DAR_U = FCh
This group of registers holds the 24-bit address of the current destination memory loca-
tion. Depending upon settings within the DMA Control registers’ DMA_CTL fields, the
24-bit address values can automatically be incremented, decremented, or unchanged fol-
lowing transfer of each byte of data. See
The two pairs of DMA Byte Count registers, listed in
number of bytes to be transferred by the DMA channels. The 16-bit value,
{DMAx_BC_H, DMAx_BC_L}, is decremented after each transfer. The DMA transfer is
complete when the value decrements to
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
X
7
The 2 sets of DMA Source address registers contain the
memory location addresses for the source of the data
transfer. The 24-bit addresses are returned by
{DMAx_SAR_U, DMAx_SAR_H, DMAx_SAR_L}, where x
is either 0 or 1.
The 2 sets of DMA Destination address registers contain
the memory location addresses for the destination of the
data transfer. The 24-bit addresses are returned by
{DMAx_DAR_U, DMAx_DAR_H, DMAx_DAR_L} where x
is either 0 or 1.
R/W
X
6
R/W
X
5
0000h
Table
R/W
X
4
. One to 65535 bytes can be transferred.
78.
R/W
X
3
Table 79
R/W
Direct Memory Access Controller
X
2
on page 145, contain the
Product Specification
R/W
X
1
R/W
X
0
eZ80190
144

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