EZ80190AZ050EC Zilog, EZ80190AZ050EC Datasheet - Page 122
EZ80190AZ050EC
Manufacturer Part Number
EZ80190AZ050EC
Description
IC WEBSERVER 50MHZ XTEMP 100lQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3123
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PS006614-1208
I
Table 56. I
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I
clock and the value in the I2Cx_CCR bits 2 to 0. The bus clock speed generated by the I
in MASTER mode is determined by the frequency of the input clock and the values in
I2Cx_CCR[2:0] and I2Cx_CCR[6:3].
The I2Cx_SRR register, listed in
any value to this register will perform a software reset of the I
2
C Software Reset Register
2
Value
00h–FFh Writing any value to this register performs a software reset of the
C sampling frequency is determined by the frequency of the eZ80190 device system
2
C bus at least ten times faster than the bus clock speed of the fastest master on the
W
X
7
Description
I
2
C module.
W
X
6
W
X
5
Table 56
W
X
4
(I2C0_SRR = CDh, I2C1_SRR = DDh)
on page 112, is a Write Only register. Writing
W
X
3
W
X
2
2
C module.
Product Specification
W
1
X
I2C Serial I/O Interface
W
2
X
0
C must sam-
2
C
112
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