Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 33

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z380 Microprocessor
Product Specification
An interrupt acknowledge transaction in response to one of /INT3-/INT1 is also five
IOCLK cycles long, unless extended by wait states. The waits are sampled and inserted at
similar locations as an interrupt acknowledge transaction is for /INT0. Note, however,
only the /INTAK signal is active with /MI, /IORQ, /IORD and /IOWR held inactive.
For either type of INTACK transaction the address bus is driven with a value which indi-
cates the type of interrupt being acknowledged as follows: A31-A6 are all one, and A3-A0
are one except for a single zero corresponding to the maskable interrupt being acknowl-
edged. Thus an /INT3 acknowledge is signaled by A3 being zero during the interrupt
acknowledge transaction, /INT2 acknowledge is signalled by A2 being zero, etc.
RETI Transactions
The RETI transaction is generated whenever an RETI instruction is executed by the Z380
MPU. This transaction is necessary because Z80 family peripherals are designed to watch
instruction fetches and take special action upon seeing a RETI instruction (this is the only
instruction that the Z80 family peripherals watch for). Since the Z380 MPU fetches
instructions using the memory control signals, a simulated RETI instruction fetch must be
placed on the bus with the appropriate I/O bus control signals. This is shown in Figure 23.
Again, note that because all I/O bus transactions start on a rising edge of IOCLK, there
may be up to n BUSCLK cycles of latency between the execution unit request for the
transaction and the transaction actually starting, where n is the programmed clock divisor
for IOCLK.
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PS010002-0708