Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 64

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PUSH/POP INSTRUCTIONS
qq
00
01
10
11
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
L2: In Long Word mode, this instruction PUSHes the register’s extended portion (register with “z” suffix) before pushing the contents of the register
L3: In Long Word mode, this instruction POPs the register’s extended portion (register with “z” suffix) after popping the contents of the register to the
L4: In Long Word mode, PUSH AF and PUSH nn instructions push 0000h onto stack in the place of the extended register portion.
L5: In Long Word mode, POP AF instruction increments SP by two after POPing 1 word of data from stack.
L6: In Long Word mode, this instruction POPs one more word from stack and loads into SR(31-16), instead of duplicating (SP+1) location into SR(31-
N:
(10): In case of AF register pair, execute time is one clock less.
Mnemonic
PUSH qq
PUSH XY
PUSH nn
PUSH SR
POP qq
POP XY
POP SR
This instruction may be used with DDIR Immediate instructions.
to the stack.
stack.
16).
In Native mode, this instruction uses addresses modulo 65536.
Pair
BC
DE
HL
AF
Symbolic
Operation
(SP-2)
(SP-1)
SP
(SP-2)
(SP-1)
SP
(SP-2)
(SP-1)
SP
(SP-2)
(SP-1)
SP
qqh
qql
SP
XYU
XYL
SP
SR(6-0)
SR(15-8)
SR(23-16)
SR(31-24)
SP
y
0
1
SP-2
SP-2
SP-2
SP-2
SP+2
SP+2
SP+2
(SP)
(SP+1)
(SP)
(SP+1)
XY
IX
IY
qql
qqh
XYL
XYU
nnl
nnh
SR(7-0)
SR(15-8)
(SP)
(SP+1)
(SP+1)
(SP+1)
Flags
S Z x H x V N C
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
P/
76 543 210
11 qq0 101
11 y11
11 100 101
11 111 101
11 110 101
11 101 101
11 000 101
11 qq0 001
11 y11
11 100 001
11 101 101
11 000 001
Opcode
n
n
101
101
HEX Bytes
ED
ED
E5
FD
C5
E1
C1
F5
# of Execute
1
2
4
2
1
2
2
Page 64 of 125
Time Notes
3+w N,L2,L4
3+w
3+w
3+w
2+r N, L3, L5
1+r
3+r
N, L4,I
N, L2
N, L2
N, L3
N, L6