PRIXP423BB Intel, PRIXP423BB Datasheet - Page 103

• Manufacturer Part Number: PRIXP423BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP423BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869741

Intel
Table 57.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
Intel Simplex Mode Values
Symbol
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
T
T
T
dholdafterwr
dval2valwrt
addr2valcs
T
T
T
T
wrpulse
rdsetup
rdhold
recov
EX_ALE is not valid in simplex mode of operation.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the expansion interface.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
Parameter
Valid address to valid chip select
Write data valid prior to EX_WR_N falling edge
Pulse width of the EX_WR_N
Valid data after the rising edge of EX_WR_N
Data valid required before the rising edge of EX_RD_N
Data hold required after the rising edge of EX_RD_N
Time required between successive accesses on the
expansion interface.
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Min.
15
1
1
1
1
0
1
Max.
16
16
4
4
4
Units
Cycles
Cycles
Cycles
Cycles
Cycles
ns
ns
Datasheet
Notes
1, 2,
3,
4,
5,
6
7
7
7
103
7