PRIXP423BB Intel, PRIXP423BB Datasheet - Page 19

• Manufacturer Part Number: PRIXP423BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP423BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869741

Status:
9.
Problem:
Implication:
Workaround:
Status:
10.
Problem:
Implication:
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Fixed.
PCI Non-Prefetch Reads (SCR 1254)
Using the non-prefetch registers to initiate read transactions on the PCI bus of the A0-step
processor can cause corrupted data. As a result of a non-prefetch read, data is returned from the
PCI bus through a FIFO and the NP_RD_DATA register located in the PCI controller. Under
certain conditions the wrong data can be returned from the NP_RD_DATA register as a result of a
read. Non-prefetch data is used to produce single cycle IXP425 network processor initiated config-
uration cycles, memory cycles, I/O cycles or any other valid PCI bus cycle types.
Non-prefetch writes are not affected by this problem. Additionally the PCI DMA channels and
memory-mapped PCI windows — used for high-bandwidth, PCI-initiated IXP425 network
processor transactions — are not affected by this problem. Target transactions directed to the
IXP425 network processor are not affected. This errata does apply to the Intel
Plane Processor A0 stepping.
Invalid data is returned from the NP_RD_DATA register for current access. Subsequent accesses
are not affected. This problem can affect the read values for configuration cycles, memory cycles,
I/O cycles and any other cycle types generated using the non-prefetch registers.
The software work around requires that the perform eight consecutive atomic non-prefetch read
operations of the desired location on the PCI bus. Furthermore, the PCI_NP_RDATA register must
be read twice, when retrieving the PCI read data. Data returned from the first seven non-prefetch
reads may be in error and is discarded. Data returned from the eighth read (the second read of the
PCI_NP_RDATA register of the eighth non-prefetch read operation) is the correct data.
This work around works under the following conditions:
In-bound PCI traffic initiated from external PCI devices does not affect the work around, so these
operations need not be restricted.
A possible hardware work around is to ensure that the IXP425 network processor’s system clock
input and PCI clock input have a fixed and known phase relationship. This would eliminate the
asynchronous “jitter” between the two signals previously mentioned. Currently, analysis has shown
that this known phase relationship sits inside a window that is too small to be implemented in a
practical application over the full range of process variation and environmental conditions.
Therefore, no hardware work around is recommended at this time.
Fixed.
Timer Status Interrupts Get Lost During MMR Writes (SCR 1653)
An interrupt becomes lost when trying to write/clear any of the timer status register bits (ost_sts)
from the Intel
hardware is trying to update this register when a time-out occurs.
The second timer interrupt will be lost.
•
•
•
•
No other intervening operations to the PCI bus can occur — during the eight non-prefetch
reads — from any AHB master.
The DMA channels in the PCI Controller must be idle.
The location to be read, on the PCI bus, must have no side-effects on reads, for example an
FIFO.
The location to be read on the PCI bus must contain static data. Alternately — if the data is
changing — application must not care which of the previous eight reads gets returned.
®
IXP42X product line and IXC1100 control plane processors in the same cycle that
Non-Core Errata
®
IXC1100 Control
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