PRIXP425BC Intel, PRIXP425BC Datasheet - Page 18

• Manufacturer Part Number: PRIXP425BC
• Description: IC NETWRK PROCESSR 400MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BC

• Processor Type: Network
• Features: XScale Core
• Speed: 400MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869083

Intel
Functional Overview
2.1.2
2.1.2.1
18
®
IXP42X Product Line and IXC1100 Control Plane Processor
In addition to having separate instruction/data memory and local-code store, the NPE core supports
hardware multi-threading with support for multiple contexts. The support of hardware
multi-threading creates an efficient processor engine with minimal processor stalls due to the
ability of the processor core to switch contexts in a single clock cycle, based on a
prioritized/preemptive basis. The prioritized/preemptive nature of the context switching allows
time-critical applications to be implemented in a low-latency fashion — which is required when
processing multi-media applications.
The NPE core also connects several hardware-based coprocessors that are used to implement
functions that are difficult for a processor to implement. These functions include:
These coprocessors are implemented in hardware, enabling the coprocessors and the NPE
processor core to operate in parallel.
The combined forces of the hardware multi-threading, local-code store, independent instruction
memory, independent data memory, and parallel processing allows the Intel XScale core to be
utilized for application purposes. The multi-processing capability of the peripheral interface
functions allows unparalleled performance to be achieved by the application running on the Intel
XScale core.
Internal Bus
The internal bus architecture of the IXP42X product line and IXC1100 control plane processors is
designed to allow parallel processing to occur and to isolate bus utilization, based on particular
traffic patterns. The bus is segmented into three major buses: the North AHB, South AHB, and
APB.
North AHB
The North AHB is a 133.32-MHz, 32-bit bus that can be mastered by the NPEs. The targets of the
North AHB can be the SDRAM or the AHB/AHB bridge. The AHB/AHB bridge allows the NPEs
to access the peripherals and internal targets on the South AHB.
Data transfers by the NPEs on the North AHB to the South AHB are targeted predominately to the
queue manager. Transfers to the AHB/AHB bridge may be “posted,” when writing, or “split,”
when reading.
When a transaction is “posted,” a master on the North AHB requests a write to a peripheral on the
South AHB. If the AHB/AHB Bridge has a free FIFO location, the write request will be transferred
from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete
the write on the South AHB, when it can obtain access to the peripheral on the South AHB. The
North AHB is released to complete another transaction.
When a transaction is “split,” a master on the North AHB requests a read of a peripheral on the
South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will be transferred
from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete
the read on the South AHB, when it can obtain access to the peripheral on the South AHB.
•
•
•
Serialization/De-serialization
DES/3DES/AES
MD5
•
•
•
CRC checking/generation
SHA-1
HDLC bit stuffing/de-stuffing
Datasheet