MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 165

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7-4
7.1.2 A d d r e s s Bus
7.1.3 A d d r e s s S t r o b e
At the beginning of a bus cycle, the size signals (SIZ0 and SIZ1) are driven
The read/write (R/W) signal determines the direction of the transfer dUring
for two consecutive write cycles.
The read-modify-write cycle signal (RMC) is asserted at.the beginning of the
first bus cycle of a read-modify-write operation and remains asserted until
the address on the bus at the beginning of a bus cycle. The address is valid
AS is a timing signal that indicates the validity of an address on the address
to transfer the entire operand, OCS is asserted only at the beginning of the
first external bus cycle. With respect to OCS, an "operand" is any entity
The function code signals (FC0-FC2) are also driven at the beginning of a
Table 4-1) to which the address applies. Five address spaces are presently
defined. Of the remaining three, one is reserved for user definition and two
are reserved by Motorola for future use. The function code signals are valid
while AS is asserted.
along with ECS and the FC0-FC2. SIZ0 and SIZ1 indicate the number of bytes
size that is less than 32 bits. Table 7-2 shows the encoding of SIZ0 and SIZ1.
These signals are valid while AS is asserted.
a bus cycle. This signal changes state, when required, at the beginning of a
cycle is preceded by a read cycle or vice versa. The signal may remain low
completion of the final bus cycle of the operation. The RM(~ signal is guar-
anteed
read-modify-write operation.
The address bus signals (A0-A31) define the address of the byte (or the most
significant byte) to be transferred during a bus cycle. The processor places
while AS is asserted.
bus and of many control signals. It is asserted one-half clock after the be-
ginning of a bus cycle.
required by the execution unit, whether a program or data item.
bus cycle. These three signals select one of eight address spaces (refer to
remaining to be transferred during an operand cycle (consisting of one or
more bus cycles) or during a cache fill operation from a device with a port
bus cycle and is valid while AS is asserted. R/W only transitions when a write
to be negated before the end of state 0 for a bus cycle following a
MC68030 USER'S MANUAL
MOTOROLA