MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 502

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

M O T O R O L A
11.6.7 Special-Purpose M O V E Instruction
The special-pu rpose MOVE timing table indicates the number of clock periods
T h e
T h e
All timing data assumes two-clock reads and writes.
%
r e a d ,
n u m b e r ,
CR - A Control Registers USP, VBR, CAAR, MSP, and ISP
CR-8 Control Registers SFC, DFC, and CACR
n
RL
*
#
needed for the processor to fetch, calculate, and perform the special-purpose
MOVE operation on the control registers or specified effective address. Foot-
n o t e s
"*
i#
*
Yo + MOVEM
Yo + MOVEM
Yo
Yo
Add Calculate Effective Address Time
Add Fetch Effective Address Time
Add Calculate Immediate Address Time
Number of Register to Transfer (n>0)
Register List
t o t a l
EXG
MOVEC
MOVEC
MOVEC
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVEP.W
MOVEP.W
MOVEP.L
MOVEP.L
MOVES
MOVES
MOVE
MOVE
SWAP
r e a d ,
MOVE
p r e f e t c h ,
i n d i c a t e
n u m b e r
p r e f e t c h ,
I n s t r u c t i o n
w h e n
Ry,Rx
Rn,Cr-A
Rn,Cr- B
CCR,Dn
CCR,Mem
Dn,CCR
EA,CCR
SR,Dn
EA,SR
EA,RL
RL,EA
Dn,(d16,An)
(d16,An),Dn
EA, Rn
Dn
Cr,Rn
Dn,(d16,An)
(d16,An),Dn
Rn,EA
An,USP
USP,An
a n d
SR,Mem
o f c l o c k
w r i t e
a n d
t o a c c o u n t
M C 6 8 0 3 0 USER'S M A N U A L
w r i t e
c y c l e s
c y c l e s is o u t s i d e
c y c l e s
f o r t h e
i s
+
g i v e n
Tail = 0 for all Wait States
MOVEM RL,EA
Head
MOVEM EA,RL
4
6
6
4
2
2
4
0
2
2
0
2
2
4
2
4
3
2
4
4
4
2
a r e
I-Cache Case T~ming -
Tail =
I-Cache Case Timing =
a p p r o p r i a t e
i n s i d e
i n c l u d e d
t h e
w > 2: (n)w+(n)(w-2)
w <- 2: (n-1)w
- -
- -
Tail
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
For n Registers (n > 0) and w Wait States
For n Registers (n > 0) and w Wait States
p a r e n t h e s e s .
t h e
i n t h e
e f f e c t i v e
I - C a c h e c a s e
8 +4n(n/0/0)
4 + 2n(0/0/n)
p a r e n t h e s e s
12(0/0/0)
10(0/0/2)
10(2/0/0)
14(0/0/4)
14(4/0/0)
4(0/0/0)
6(0/0/0)
4(0i0/0)
4(0/0/0)
4(0/0/0)
4(0/0/0)
4(0/0/0)
4(0/0/0)
6(0/O/O)
4(010/0)
4(01011)
4(0/0/1)
8(Q/0/0)
7(1/0/0)
5(0/0/1)
w > 2: (8+4n)+(w-2)n
w > 2: (4+2n)+(n- 1)w+(w-2)
w ~< 2: (8+4n)
w ~< 2: (4+2n)+(n- 1)w
t o t a l
T h e
a d d r e s s
N o - C a c h e C a s e
4+ 2n(0/1/n)
8 +4n(n/1/0)
c l o c k
12(0/I/0)
10(0/2/0)
10(0/1/2)
10(2/1/0)
14(0/1/4)
14(4/1/0)
n u m b e r
4(0/1/0)
6(0/1/0)
6(0/1/0)
4(01110)
4(0/1/0)
4(0/1/0)
6(0/1/11
5(01111)
7(1/1/0)
4(0/1/0)
4(0/1/0)
4(0/1/0)
4(0/1/0)
5(0/1/1)
a s ( r / p / w ) .
t i m e s .
c y c l e
11-39
o f
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