MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 240

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
t h a t cycle m a y be t e r m i n a t e d p r e m a t u r e l y .
T h e t e r m i n a t i o n s i g n a l f o r a s y n c h r o n o u s cycle is STERM. An a n a l o g o u s set
o f bus cycle t e r m i n a t i o n cases exists in r e l a t i o n s h i p to STERM assertion.
cycle. STERM has s e t u p t i m e (#60) and h o l d t i m e (#61) r e q u i r e m e n t s relative
to each rising e d g e of the p r o c e s s o r clock w h i l e AS is asserted. Bus e r r o r
and retry t e r m i n a t i o n s d u r i n g b u r s t cycles o p e r a t e as d e s c r i b e d in 6.1.3.2
B U R S T M O D E FILLING, 7.5.1 Bus Error, and 7.5.2 Retry Operation.
LEGEND:
T a b l e 7-8 s h o w s v a r i o u s c o m b i n a t i o n s of c o n t r o l s i g n a l s e q u e n c e s and the
MC68030 Electrical Specifications.
after AS. If D S A C K x or BERR r e m a i n a s s e r t e d i n t o $2 of t h e n e x t bus cycle,
N o t e t h a t STERM and D S A C K x m u s t n e v e r b o t h be asserted in the s a m e
r e s u l t i n g bus cycle t e r m i n a t i o n s . To e n s u r e p r e d i c t a b l e o p e r a t i o n , BERR and
H A L T s h o u l d be n e g a t e d a c c o r d i n g to t h e s p e c i f i c a t i o n s in MC68030EC/D,
A -- Signal is asserted in this bus state
X -- Don't care
S -- Signal was asserted in previous state anti remains asserted in this state
N -- The number of current even bus state (e.g., $2, $4, etc.)
NA-- Signal is not asserted in this state
Case
No.
4
2
3
5
6
1
Control
HALT
DSACKx
BERR
HALT
DSACKx
BERR
HALT
DSACKx
BERR
HALT
DSACKx
BERR
HALT
DSACKx
BERR
HALT
DSACKx
BERR
Signal
Table 7-8. DSACK, BERR, and HALT Assertion Results
Asserted on Rising
NA/A
NA/A
A/S
A/S
NA
NA
NA
NA
NA
Edge of State
NA
NA
NA
A
A
A
A
A
N
A
MC68030 USER'S MANUAL
N+2
NA
NA
NA
NA
A
X
X
A
X
A
S
S
X
X
S
S
S
S
Terminate and take bus error exception, possibly
Terminate and take bus error exception, possibly
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
~ormal cycle terminate and continue.
Xormal cycle terminate and halt. Continue when HALT
D S A C K x , BERR, and H A L T m a y be n e g a t e d
deferred.
deferred.
negated.
Result
7-79
7