MC68EN360AI33L Freescale Semiconductor, MC68EN360AI33L Datasheet
MC68EN360AI33L
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... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL INFORMATION Asynchronous HDLC MC68360 ASYNC HDLC Protocol Microcode For More Information On This Product, User’s Manual Rev 1.1 January 24, 1996 Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Asynchronous HDLC 1 ASYNC HDLC Controller Overview 2 ASYNC HDLC Controller Key Features 2.1 ASYNC HDLC Channel Frame Transmission Processing 2.2 ASYNC HDLC Channel Frame Reception Processing 2.3 Transmitter Transparency Encoding 2.4 Receiver Transparency Decoding 2.4.1 Receive Flowchart 2.4.2 Cases not covered by RFC 1549 2 ...
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... Freescale Semiconductor, Inc. 9 Differences Between HDLC and ASYNC-HDLC 9.1 Max Received Frame Length Counter 9.2 Frame termination due to error 9.3 Commands 9.4 Automatic Error Counters 9.5 Noisy Characters Appendix A - Microcode Initialization Procedure A.1 Initialization Procedure for QUICC Version $0001 A.2 Initialization Procedure for QUICC Revision $0002 A ...
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... Freescale Semiconductor, Inc. 1 ASYNC HDLC Controller Overview Asynchronous HDLC is a frame-based protocol which uses HDLC framing techniques in conjunction with UART-type characters. This protocol is typically used as the physical layer for the Point-to-Point (PPP) protocol. While this protocol can be implemented by the UART controller on the QUICC in conjunction with the CPU32 more efficient and less com- pute-intensive for the CPU to allow the Communications Processor Module (CPM) of the QUICC to perform the framing and transparency functions of the protocol ...
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... Freescale Semiconductor, Inc. While the ASYNC HDLC controller is transmitting data from the buffers, it automatically per- forms the transparency encoding specified by the protocol. This encoding is described in de- tail in section 2.3 on page 5. If the user wishes to re-arrange the transmit queue before the Communications Processor (CP) has completed transmission of all buffers, the user should issue the STOP TRANSMIT command ...
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... Freescale Semiconductor, Inc. • The byte has a value between 0x00 and 0x1F and the corresponding bit in the TX Con- trol Character Table is set. If the outgoing byte matches one of these three criteria, a two-byte sequence is transmitted in place of the byte. This sequence consists of the Control-Escape Character (0x7D) fol- lowed by the original byte exclusive-or’ ...
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... Freescale Semiconductor, Inc. 2.4.1 Receive Flowchart Check Rx ACCM mapped? T discard F char xornext:=1 discard char 2.4.2 Cases not covered by RFC 1549 The following cases are not covered by RFC 1549. • 0x7D is followed by a control character, and the control character is NOT mapped, the control character itself will be “modified” by the xor process assumed that this will be caught by the CRC check. • ...
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... Freescale Semiconductor, Inc. —Carrier Detect Lost —Receiver Overrun • If the invalid sequence (0x7D, 0x7D) is received, the first control escape character will be discarded and the second will be unconditionally exclusive-or’ed with 0x20. This se- quence will thus be stored in the buffer descriptor as (0x5D). 2.5 Implementation Specifics related to Asynchronous HDLC 2 ...
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... Freescale Semiconductor, Inc. 3 Microcode Use The Asynchronous HDLC microcode must be loaded into QUICC DPRAM at initialization time ‘small’ (512 byte) microcode and thus will consume the memory area from DPR- BASE + $000 to DPRBASE + $1FF. In addition, the “Microcode Scratch” area of the memory map from DPRBASE + $600 to DPRBASE + $6FF will be inaccessible to the user. (See Sec- tion 3.1 of the MC68360 User’ ...
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... Freescale Semiconductor, Inc. Table 1. ASYNC HDLC-Specific Parameters Address Name SCC Base+46 Zero SCC Base+48 Reserved SCC Base+4A RFTHR SCC Base+4C Reserved SCC Base+4E Reserved SCC Base+50 TXCTL_TBL SCC Base+54 RXCTL_TBL SCC Base+58 SCC Base+5A Note: Entries in boldface must be initialized by the user. ...
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... Freescale Semiconductor, Inc. 4.2 Configuring the General SCC Parameters The general SCC parameters can be configured as described on pages 7-112 through 7- 131 of the QUICC User’s Manual except for the following changes: 4.2.1 GSMR Register The General SCC Mode Register bits are the same except for: RFW— ...
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... Freescale Semiconductor, Inc. pins. A maskable interrupt may be generated upon a status change in either one of those lines. 5.1 ASYNC HDLC Command Set The following commands are issued to the Command Register (CR) documented in Section 7.1 of the MC68360 User’s Manual. 5.1.1 Transmit Commands After a hardware or software reset and the enabling of the channel in the SCC mode regis- ter, the channel is in the transmit enable mode and starts polling the first BD in the table ev- ery 8 transmit bit-times, or immediately if the TOD bit in the TODR is set ...
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... Freescale Semiconductor, Inc. 5.1.2 Receive Commands After a hardware or software reset and the enabling of the channel by its SCC mode register, the channel is in the receive enable mode and will use the first BD in the table. ENTER HUNT MODE Command This command is not supported by the ASYNC HDLC controller. ...
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... Freescale Semiconductor, Inc. has the highest priority. The rest of the frame is lost and other errors are not checked in that frame. The receiver then searches for the next frame once CD is reasserted. Abort Sequence An abort sequence is detected by the ASYNC HDLC controller when the ABORT sequence is received (0x7d followed by 0x7e) ...
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... Freescale Semiconductor, Inc. bits 15-13, 10-9, 7-5—Reserved, should be written with zeros. GLr—Glitch clock glitch was detected by this SCC on the receive clock GLt—Glitch clock glitch was detected by this SCC on the transmit clock IDL—Idle Sequence Status Changed A change in the status of the serial line was detected. The real-time status of the line may be read in SCCS. TXE— ...
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... Freescale Semiconductor, Inc. of the current character, the next full character may be sent, and then transmission will be stopped.) When CTS is asserted once more, transmission will continue where it left off. No CTS lost error will be reported. No characters except idles will be transmitted while CTS is negated. ...
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... Freescale Semiconductor, Inc. L—Last in frame This bit is set by the ASYNC HDLC controller when this buffer is the last in a frame. This implies the reception of a closing flag or reception of an error, in which case one or more of the BRK, CD, OV, and AB bits are set. The ASYNC HDLC controller will write the num- ber of frame octets to the data length field. 0— ...
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... Freescale Semiconductor, Inc. have any characters in it and the “Data Length” field will contain a value equal to the sum of the “Data Length” fields of the other buffer descriptors in the frame. The actual amount of memory allocated for this buffer should be greater than or equal to the contents of the MRBLR ...
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... Freescale Semiconductor, Inc. L—Last 0— This is not the last buffer in the current frame. 1— This is the last buffer in the current frame. The proper CRC and closing FLAG will be transmitted following the transmission of the last data byte. CM—Continuous Mode 0— Normal operation. ...
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... Freescale Semiconductor, Inc. tial character will NOT be written to memory, (and thus the octet count will only reflect the number of bytes written to memory). 9.3 Commands The following commands are not supported: • GRACEFUL STOP TRANSMIT • ENTER HUNT MODE 9.4 Automatic Error Counters The Automatic Error Counters in HDLC mode (CRCEC, ABTEC, etc ...
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... Freescale Semiconductor, Inc. Appendix A - Microcode Initialization Procedure The initialization procedure and S-Record will vary depending upon the QUICC ROM revi- sion that the microcode was written for. Be sure to check the Rev_Num register in the Misc_Base area to determine which S-Record to load. A.1 Initialization Procedure for QUICC Version $0001 Revision $0001 silicon can be identified by a value of $0001 in the Rev_Num register ...
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... Freescale Semiconductor, Inc. A.3 Initialization Procedure for QUICC Version $0003 Revision $0003 silicon can be identified by a value of $0003 in the Rev_Num register. 1. Download the supplied S-Record for Rev $0003 onto the QUICC that is going to be running the ASYNC-HDLC microcode package. The S-Record was created assuming that the base of Dual-Port RAM on the selected QUICC starts at $20000 ...
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... Freescale Semiconductor, Inc. Appendix B - Programming Example The following list is a suggested initialization sequence when using ASYNC-HDLC. This as- sumes that you have already followed the initialization procedure in Section 3.1. 1. Initialize the SDCR register. 2. Configure Port A and Port C pints to enable RXD, TXD, CTS, CD, and CTS. (This as- sumes you are using NMSI mode ...
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... Freescale Semiconductor, Inc. Appendix C - References [1] “RFC 1549 - PPP in HDLC Framing”, W. Simpson, December 1993. [2] “RFC 1548 - The Point-to-Point Protocol (PPP)”, W. Simpson, December 1993. These two documents can be obtained via anonymous FTP from nic.ddn.mil in the /rfc di- rectory. MOTOROLA For More Information On This Product, Go to: www ...