MC68EN360AI33L Freescale Semiconductor, MC68EN360AI33L Datasheet - Page 19

• Manufacturer Part Number: MC68EN360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 33MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

L—Last
CM—Continuous Mode
The following status bits are written by the ASYNC HDLC controller after it has finished
transmitting the associated data buffer.
CTS—CTS Lost
Data Length
Tx Data Buffer Pointer
9 Differences Between HDLC and ASYNC-HDLC
In order to fit this controller into the “small” microcode area, various compromises had to be
made. Thus, the ASYNC HDLC controller does not work exactly like the standard HDLC
controller. This section details some of the differences.
9.1 Max Received Frame Length Counter
There is no maximum received frame length counter in the ASYNC-HDLC controller. There-
fore, the controller will receive ALL characters between opening and closing flags. There is
no way to have the controller stop writing to memory. This in no way affects the number of
bytes received into a specific buffer descriptor. This just means that a frame that is over the
maximum length will be received into memory in its entirety.
9.2 Frame termination due to error
If frame reception terminates due to an error condition (CD lost, Overrun, break character
received), the character being received at the time that the error occurred will not be written
into memory. For example, if a CD lost error occurred, the frame will be closed and the par-
MOTOROLA
CTS in NMSI mode was lost during frame transmission. If data from more than one buffer
is currently in the FIFO when this error occurs, this bit will be set in the TX BD that is cur-
rently open.
Data length is the number of bytes the ASYNC-HDLC controller should transmit from this
BD’s data buffer. It is never modified by the CP. The value of this field must be greater
than zero.
The transmit buffer pointer, which contains the address of the associated data buffer, may
be even or odd. The buffer may reside in either internal or external memory. This value is
never modified by the CP.
0— This is not the last buffer in the current frame.
1— This is the last buffer in the current frame. The proper CRC and closing FLAG will
0— Normal operation.
1— The R-bit is not cleared by the CP after this BD is closed, allowing the associated
be transmitted following the transmission of the last data byte.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Asynchronous HDLC
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