MC68EN360AI33L Freescale Semiconductor, MC68EN360AI33L Datasheet - Page 9

• Manufacturer Part Number: MC68EN360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 33MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3 Microcode Use
The Asynchronous HDLC microcode must be loaded into QUICC DPRAM at initialization
time. It is a ‘small’ (512 byte) microcode and thus will consume the memory area from DPR-
BASE + $000 to DPRBASE + $1FF. In addition, the “Microcode Scratch” area of the memory
map from DPRBASE + $600 to DPRBASE + $6FF will be inaccessible to the user. (See Sec-
tion 3.1 of the MC68360 User’s Manual for more information.)
The memory areas listed above are physically locked once the ERAM bit is set in the RCCR
register. Thus, any reads or writes to that area by the CPU32+ will have no effect on memory
or the microcode.
3.1 Initialization Procedure
See Appendix A - Microcode Initialization Procedure, for instructions on how to load and ini-
tialize the microcode.
3.2 Performance
At 25Mhz, an aggregate Asynchronous HDLC data rate of 3 Mbps divided among the 4
SCCs consumes 100% of the processing power of the RISC communications engine. If only
a percentage of the total available Asynchronous HDLC data rate is used, the remaining
RISC processing power can be used to run other protocols on other channels.The following
table illustrates some example configurations of the QUICC using the ASYNC-HDLC micro-
code. This table can be used in conjunction with the table in Appendix A of the MC68360
User’s Manual to determine if your desired configuration can be handled by the QUICC.
4 ASYNC HDLC Memory Map
4.1 ASYNC HDLC-Specific Parameters
When configured to operate in ASYNC HDLC mode, the QUICC overlays the structure illus-
trated listed in Table 7-5 with the ASYNC HDLC-specific parameters described in Table 1.
MOTOROLA
The “Risc Bandwidth Consumed” column indicates the amount of RISC bandwidth
being consumed by the ASYNC HDLC controller only.
SCC Base+34
SCC Base+38
SCC Base+3C
SCC Base+3E
SCC Base+40
SCC Base+42
SCC Base+44
AHDLC Channels
1 x 115 Kbit/s
2 x 230 Kbit/s
3 x 230 Kbit/s
Address
C_MASK
C_PRES
Reserved
Reserved
Table 1. ASYNC HDLC-Specific Parameters
Freescale Semiconductor, Inc.
Risc Bandwidth
Consumed (est)
For More Information On This Product,
Name
15%
24%
4%
Go to: www.freescale.com
Width
Word
Word
Word
Word
Word
Long
Long
1 x 10Mbit Ethernet, 2 x 1.5 Mbit HDLC, 9.6 Kbit SMC UART
1 x 10Mbit Ethernet, 1 x 1.5 Mbit HDLC, 9.6 Kbit SMC UART
1 x 5Mbit HDLC, 2 x 9.6 Kbit SMC UART
Possible Configuration of Other Channels
CRC Constant
CRC Preset
Description
Asynchronous HDLC
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