MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 51

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

indexing into the on-chip instruction and data caches. The MMU MDIS signal dynamically
disables address translation for emulation and diagnostic support.
Figure 3-1 illustrates the MMUs contained in the two memory units, one for instructions
(supporting instruction prefetches) and one for data (supporting all other accesses). Each
unit contains an MMU, main cache, and snoop controller. The corresponding MMUs
contain two transparent translation registers, which identify blocks of memory that can be
accessed without translation. The MMUs also contain control logic and corresponding
address translation caches (ATCs) in which recently used logical-to-physical address
translations are stored. The data memory unit contains a data write and data read buffer,
and the instruction memory unit contains an instruction line read buffer. These buffers
temporarily hold data until an opportune moment arises to write the data to external
memory or read the operand/instruction into the integer unit.
The principal MMU function is to translate logical addresses to physical addresses using
translation tables stored in memory. As the MMU receives a logical address from the
integer unit, it searches its ATC for the corresponding physical address using the upper
3-2
CONVERT
FLOATING-
EXECUTE
WRITE-
BACK
POINT
UNIT
INSTRUCTION
CALCULATE
EXECUTE
INTEGER
DECODE
WRITE-
FETCH
FETCH
BACK
UNIT
EA
EA
Freescale Semiconductor, Inc.
Figure 3-1. Memory Management Unit
For More Information On This Product,
M68040 USER'S MANUAL
Go to: www.freescale.com
INSTRUCTION
DATA
ATC
INSTRUCTION MEMORY UNIT
ATC
INSTRUCTION DATA BUS
OPERAND DATA BUS
DATA MEMORY UNIT
MMU/CACHE/SNOOP
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION
CONTROLLER
DATA
INSTRUCTION
CACHE
CACHE
DATA
INSTRUCTION
ADDRESS
ADDRESS
DATA
B
U
S
C
O
N
T
R
O
E
R
L
L
MOTOROLA
ADDRESS
CONTROL
SIGNALS
DATA
BUS
BUS
BUS