MC68020FE20E Freescale Semiconductor, MC68020FE20E Datasheet - Page 145

• Manufacturer Part Number: MC68020FE20E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
The priority scheme is very important in determining the order in which exception handlers
execute when several exceptions occur at the same time. As a general rule, the lower the
priority of an exception, the sooner the handler routine for that exception executes. For
example, if simultaneous trap, trace, and interrupt exceptions are pending, the exception
processing for the trap occurs first, followed immediately by exception processing for the
trace, and then for the interrupt. When the processor resumes normal instruction
execution, it is in the interrupt handler, which returns to the trace handler, which returns to
the trap exception handler. This rule does not apply to the reset exception; its handler is
executed first even though it has the highest priority because the reset operation clears all
other exceptions.
6.1.12 Return from Exception
After the MC68020/EC020 has completed exception processing for all pending
exceptions, it resumes normal instruction execution at the address in the vector for the last
exception processed. Once the exception handler has completed execution, the processor
must return to the system context prior to the exception (if possible). The RTE instruction
returns from the handler to the previous system context for any exception.
When the processor executes an RTE instruction, it examines the stack frame on top of
the active supervisor stack to determine if it is a valid frame and what type of context
restoration it requires. The following paragraphs describe the processing for each of the
stack frame types; refer to 6.3 Coprocessor Considerations for a description of the
stack frame type formats.
For a normal four-word frame, the processor updates the SR and PC with the data read
from the stack, increments the stack pointer by eight, and resumes normal instruction
execution.
For the throwaway four-word frame, the processor reads the SR value from the frame,
increments the active stack pointer by eight, updates the SR with the value read from the
stack, and then begins RTE processing again, as shown in Figure 6-7. The processor
reads a new format word from the stack frame on top of the active stack (which may or
may not be the same stack used for the previous operation) and performs the proper
operations corresponding to that format. In most cases, the throwaway frame is on the
interrupt stack and when the SR value is read from the stack, the S and M bits are set. In
that case, there is a normal four-word frame or a ten-word coprocessor midinstruction
frame on the master stack. However, the second frame may be any format (even another
throwaway frame) and may reside on any of the three system stacks.
For the six-word stack frame, the processor restores the SR and PC values from the
stack, increments the active supervisor stack pointer by 12, and resumes normal
instruction execution.
6-20
M68020 USER’S MANUAL
MOTOROLA
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