MC68020FE20E Freescale Semiconductor, MC68020FE20E Datasheet - Page 284

• Manufacturer Part Number: MC68020FE20E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

AC ELECTRICAL CHARACTERISTICSÑREAD AND WRITE CYCLES
NOTES:
10-10
10. These specifications allow system designers to guarantee that an alternate bus master has stopped driving the
11. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS (allowing
(Concluded)
1. This number can be reduced to 5 ns if strobes have equal loads.
2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACK» low to data setup time (#31) and
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or DSACK1 to
4. This specification applies to the first (DSACK0 or DSACK1) DSACK» signal asserted. In the absence of
5. DBEN may stay asserted on consecutive write cycles.
6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded, BG may
7. This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit
8. This specification guarantees operation with the MC68881/MC68882, which specifies a minimum time for DS
9. This specification allows a system designer to guarantee data hold times on the output side of data buffers that
DSACK» low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in clock low
setup time (#27) for the following clock cycle, and BERR must only satisfy the late BERR low to clock low setup
time (#27A) for the following clock cycle.
DSACK0 asserted; specification #47A must be met by DSACK0 or DSACK1.
DSACK», BERR is an asynchronous input using the asynchronous input setup time (#47A).
be reasserted.
followed immediately by a cache miss or operand cycle.
negated to AS asserted (specification #13A in MC68881UM/AD, MC68881/MC68882 Floating-Point
Coprocessor User's Manual). Without this specification, incorrect interpretation of specifications #9A and #15
would indicate that the MC68020/EC020 does not meet the MC68881/MC68882 requirements.
have output enable signals generated with DBEN.
bus when the MC68020/EC020 regains control of the bus after an arbitration sequence.
7 ns for a gate delay) and still meet the CS to DS setup time requirement (specification 8B of MC68881UM/AD,
MC68881/MC68882 Floating-Point Coprocessor User's Manual).
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USERÕS MANUAL
Go to: www.freescale.com
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