MC68020FE20E Freescale Semiconductor, MC68020FE20E Datasheet - Page 50

• Manufacturer Part Number: MC68020FE20E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
When initiating a bus cycle, the MC68020 asserts ECS in addition to A1–A0, SIZ1, SIZ0,
FC2–FC0, and R/W . ECS can be used to initiate various timing sequences that are
eventually qualified with AS. Qualification with AS may be required since, in the case of an
internal cache hit, a bus cycle may be aborted after ECS has been asserted. During the
first MC68020 external bus cycle of an operand transfer, OCS is asserted with ECS. When
several bus cycles are required to transfer the entire operand, OCS is asserted only at the
beginning of the first external bus cycle. With respect to OCS, an “operand” is any entity
required by the execution unit, whether a program or data item. Note that ECS and OCS
are not implemented in the MC68EC020.
The FC2–FC0 signals select one of eight address spaces (see Table 2-1) to which the
address applies. Five address spaces are presently defined. Of the remaining three, one
is reserved for user definition, and two are reserved by Motorola for future use. FC2–FC0
are valid while AS is asserted.
The SIZ1 and SIZ0 signals indicate the number of bytes remaining to be transferred
during an operand cycle (consisting of one or more bus cycles) or during a cache fill
operation from a device with a port size that is less than 32 bits. Table 5-2 lists the
encoding of SIZ1 and SIZ0. SIZ1 and SIZ0 are valid while AS is asserted.
The R/W signal determines the direction of the transfer during a bus cycle. When required,
this signal changes state at the beginning of a bus cycle and is valid while AS is asserted.
R/W only transitions when a write cycle is preceded by a read cycle or vice versa. This
signal may remain low for two consecutive write cycles.
The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write
operation and remains asserted until completion of the final bus cycle of the operation.
The RMC signal is guaranteed to be negated before the end of state 0 for a bus cycle
following a read-modify-write operation.
5.1.2 Address Bus
A31–A0 (for the MC68020) or A23–A0 (for the MC68EC020) define the address of the
byte (or the most significant byte) to be transferred during a bus cycle. The processor
places the address on the bus at the beginning of a bus cycle. The address is valid while
AS is asserted. In the MC68EC020, A31–A24 are used internally, but not externally.
5.1.3 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and of
many control signals. It is asserted one-half clock after the beginning of a bus cycle.
5.1.4 Data Bus
D31–D0 comprise a bidirectional, nonmultiplexed parallel bus that contains the data being
transferred to or from the processor. A read or write operation may transfer 8, 16, 24, or
32 bits of data (one, two, three, or four bytes) in one bus cycle. During a read cycle, the
data is latched by the processor on the last falling edge of the clock for that bus cycle. For
MOTOROLA
M68020 USER’S MANUAL
5- 3
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