MPC8347EVVAJFB Freescale Semiconductor, MPC8347EVVAJFB Datasheet

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... To locate published errata or updates for this document, refer to the MPC8347EA product summary page on our website, as listed on the back cover of this document, or contact your local Freescale sales office. © 2006–2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8347EAEC Rev. 11, 10/2010 Contents 1 ...

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... MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev NOTE e300 Core 2 C Interrupt 32KB 32KB Controller D-Cache I-Cache 10/100/1000 10/100/1000 Ethernet Ethernet Figure 1. MPC8347EA Block Diagram for Figure 1 shows the major functional DDR SDRAM Local Bus Controller SEQ PCI DMA Freescale Semiconductor ...

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... Memory prefetching of PCI read accesses and support for delayed read transactions — Posting of processor-to-PCI and PCI-to-memory writes — On-chip arbitration supporting five masters on PCI — Accesses to all PCI address spaces — Parity supported — Selectable hardware-enforced coherency MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Overview 3 ...

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... USB on-the-go mode with both device and host functionality — Complies with USB specification Rev. 2.0 — Can operate as a stand-alone USB device – One upstream facing port – Six programmable USB endpoints MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Redirects interrupts to external INTA pin in core disable mode. — Unique vector number for each interrupt source • Dual industry-standard I — Two-wire interface — Multiple master support 2 — Master or slave I C mode support MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 2 C interfaces Overview 5 ...

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... I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev C-1 EPROM by boot sequencer embedded Freescale Semiconductor ...

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... IN REF 6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol ...

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... Recommended Unit Value 1.3 V ± 1.2 V ± 1.3 V ± 1.2 V ± 2.5 V ± 125 mV V 1.8 V ± 3.3 V ± 330 mV V 2.5 V ± 125 mV 3.3 V ± 330 mV V 2.5 V ± 125 mV 3.3 V ± 330 /OV / Freescale Semiconductor Notes — — — — ...

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... To minimize the time that I/O pins are actively driven recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 11 ns (Min) +7 ...

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... Table 5. = 105°C, and a Dhrystone benchmark J target, and I 105°C, and 105°C, and a Dhrystone benchmark J = 105°C, and an J Freescale Semiconductor Unit ...

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... MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits TSEC I/O MII load = 25 pF GMII or TBI RGMII or RTBI USB 12 MHz 480 MHz Other I/O 1 TBGA package only. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor DDR2 DDR1 (3.3 V) (3.3 V) (1.8 V) (2.5 V) ...

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... KHK CLKIN — — Min Max 2 0 –0.3 0 — ± — ± — ±50 IN Table 7 provides the clock input Typical Max Unit — 66 MHz — — ns 1.0 2.3 ns — — ±150 ps Freescale Semiconductor Unit V V μA μA μA Notes 1, 6 — ...

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... Table 9. RESET Pins DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current 2 Output high voltage Output low voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV DD Symbol Min t — G125 t — ...

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... MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev (continued) Symbol Condition Min 3 not relevant for those pins. OH Min 512 — 1 Max Unit — 0.4 V Max Unit Notes — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — PCI_SYNC_IN — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — ns — — PCI_SYNC_IN Freescale Semiconductor ...

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... Input high voltage Input low voltage Output leakage current Output high current (V = 1.420 V) OUT MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 11. PLL and DLL Lock Times Min — 7680 Section 19, “Clocking.” (typ) = 2.5 V and DDR2 SDRAM is GV ...

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... OUT DD (typ) = 1.8 V (continued) DD — (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT (typ Max Unit 2.625 V 0.51 × 0.04 V REF – 0.18 V REF μA –9.9 — mA — Freescale Semiconductor — Notes 1 1 Notes — — 4 — — ...

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... AC timing specifications for the DDR SDRAM when GV Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions with GV Parameter AC input low voltage AC input high voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor (typ Symbol C IO ...

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... T is the clock period and abs (t CISKEW t MCK DISKEW Figure 4. DDR Input Timing Diagram Max Unit ps 600 750 750 750 . This can be DISKEW ) is the absolute CISKEW timing parameter. DISKEW t DISKEW Freescale Semiconductor Notes — — — ...

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... MDQ/MECC/MDM output setup with respect to MDQS 400 MHz 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 400 MHz 333 MHz MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor of (1.8 or 2.5 V) ± 5 Symbol Min t 5 MCK t 7 ...

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... MCK MCK –0.6 0.6 ns memory clock reference (K) goes MCK describes the DDR timing (DD) from the DDKHMH can be modified through control of the DDKHMH follows the DDKHMP DDKHMH Freescale Semiconductor Notes 6 6 for inputs DDKHAS ). DDKHMH ...

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... DC electrical characteristics for the DUART interface of the MPC8347EA. Table 21. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (0.8 V ≤ V ≤ MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t MCK t ,t DDKHAS DDKHCS t ,t ...

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... Symbol V V Table 22. DUART AC Timing Specifications Parameter th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Min Max OV – 0.2 — — 0.2 OL Value Unit 256 baud > 1,000,000 baud 16 — Section 8.3, Freescale Semiconductor Unit V V Notes — ...

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... The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 24. The RGMII and RTBI signals in Symbol Conditions 2 LV — ...

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... Figure 8. GMII Transmit AC Timing Diagram Min Typ Max — 8.0 — 43.75 — 56.25 0.5 — 5.0 — — 1.0 — — 1.0 — 8.0 — 45 — 55 for inputs and symbolizes GMII transmit timing (GT) GTKHDV clock GTX t GTXR Freescale Semiconductor Unit ...

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... GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 9 shows the GMII receive AC timing diagram. G RX_CLK RXD[7:0] RX_DV RX_ER MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t GRX t ...

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... For example MTX t t MTXF MTXH t MTKHDX Figure 10. MII Transmit AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 for inputs symbolizes MII transmit timing MTKHDX t MTXR Freescale Semiconductor Unit MTX ...

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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 11 provides the AC test load for TSEC. Output Figure 12 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t MRX t MRX t ...

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... Min Typ Max — 8.0 — 40 — 60 1.0 — 5.0 — — 1.0 — — 1.0 — 8.0 — 45 — 55 symbolizes the TBI transmit TTKHDV (K) going high (H) until TTX represents the TBI (T) transmit TTX t TTXR t TTKHDX Freescale Semiconductor Unit for inputs ...

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... Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0. Figure 14 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t ...

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... RGTH RGT RGTH RGT t RGTR t RGTF 6 t G12 t /t G125H G125 Min Typ Max Unit –0.5 — 0.5 1.0 — 2.8 7.2 8.0 8 — — 0.75 — — 0.75 — 8.0 — 47 — the lowest speed transitioned. RGT Freescale Semiconductor ...

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... MDIO and MDC are provided in Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] ...

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... Table 2. Typ Max Unit Notes 2.5 — MHz 400 — ns — — ns — 170 ns — — ns — — ns — Freescale Semiconductor Unit μA μA Unit μA μA 2 — — 3 — — — ...

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... Figure 16 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 16. MII Management Interface Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor is 3.3 V ± 10% or 2.5 V ± 5 Symbol Min t — MDHF (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... OV – 0.2 — DD — 0.2 Min Max Unit 15 — — — ns — — ns for inputs symbolizes USB timing (US) for USIXKH symbolizes USKHOX of the signal in question for 3 Freescale Semiconductor Unit V V μ Notes 2–5 2–5 2–5 2–5 2–5 ...

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... Table 37. Local Bus DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μA Low-level output voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor = 50 Ω Ω Figure 17. USB AC Test Load t USIVKH t t ...

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... Unit Notes 7.5 — 1.5 — 2.2 — 1.0 — 1.0 — 1.5 — — 2.5 — — 4.5 ns — — 4.5 ns — — 4 — 4 — — — 3 for inputs symbolizes local bus timing (LB) LBIXKH1 of the signal in question for 3 Freescale Semiconductor ...

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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 19 provides the AC test load for the local bus. Output MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 1 Symbol t LBK t ...

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... Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev LBIVKH t LBKHOV t LBKHOZ t t LBKHOV LBKHOX t LBKHOZ t t LBKHOV LBKHOX t LBOTOT t LBKHLR t LBIXKH t LBKLOV t t LBKHOZ LBKLOV t t LBKLOV LBOTOT t LBIXKH t LBIXKH t LBIXKH t LBIVKH t LBIVKH Freescale Semiconductor ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ t LBKLOV t LBIVKH t t LBKHOZ t LBKLOV t LBIXKH t LBIXKH LBIVKH Freescale Semiconductor ...

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... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8347EA. Table 40. JTAG Interface DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current Output high voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... JTDXKH TMS, TDI t JTIXKH t JTKLDV TDO t JTKLOV t JTKLDX TDO t JTKLOX Min Max — 0.5 — 0.4 Figure 27 through 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 4 — — 10 — — 2 — Freescale Semiconductor Unit V V — — — — ...

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... Figure 27 provides the JTAG clock input timing diagram. JTAG External Clock Figure 27. JTAG Clock Input Timing Diagram Figure 28 provides the TRST timing diagram. TRST MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 2). 2 Symbol t JTKLDZ TDO t JTKLOZ (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 29. Boundary-Scan Timing Diagram VM t JTIVKH t JTKLOV t JTKLOZ VM = Midpoint Voltage ( JTDXKH Input Data Valid Output Data Valid VM t JTIXKH Input Data Valid Output Data Valid Freescale Semiconductor ...

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... Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time:CBUS compatible masters bus devices MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 2 C interface of the MPC8347EA. 2 Table 42 Electrical Characteristics of 3.3 V ± 10%. DD Symbol 0.7 × ...

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... OV V — symbolizes I C timing (I2) with I2DVKH clock reference (K) going to the high (H) I2C symbolizes I I2PVKH (min) of the SCL signal) to bridge the SCL signal. I2CL AC parameter. I2CF Ω I2KHKL I2CF t I2CR t I2PVKH P Freescale Semiconductor Unit ns μs μ for inputs 2 C clock I2C S ...

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... Table 45. PCI AC Timing Specifications at 66 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 44. PCI DC Electrical Characteristics Symbol Test Condition ≥ (min) or ...

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... PCI timing (PC) with respect to the time hard reset (R) went PCRHFV = 50 Ω Ω Figure 33. PCI AC Test Load 1 (continued) Max Unit Notes — for inputs symbolizes PCI timing (PC) with PCIVKH , reference (K) going SYS Max Unit Notes — — — for inputs symbolizes PCI timing (PC) with PCIVKH , reference (K) going SYS Freescale Semiconductor ...

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... Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t PCIVKH Figure 34. PCI Input AC Timing Diagram t PCKHOV Figure 35. PCI Output AC Timing Diagram Symbol ...

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... TIWID Symbol Condition V — — — – Symbol t PIWID ns to ensure proper operation. PIWID 2 Min Unit 20 ns Min Max Unit 2 0 –0.3 0.8 V μA — ±5 2.4 — V — 0.5 V — 0 Min Unit 20 ns Freescale Semiconductor ...

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... SPI This section describes the SPI DC and AC electrical specifications. 17.1 SPI DC Electrical Characteristics Table 53 provides the SPI DC electrical characteristics. Parameter Input high voltage Input low voltage MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Condition V — — — ...

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... For example Ω Figure 36. SPI AC Test Load Min Max — ±5 2.4 — — 0.5 — 0 Min Max — 6 0.5 — — — 4 — 0 — 4 — 2 — symbolizes the internal timing NIKHOX Ω L Freescale Semiconductor Unit μ Unit for inputs ...

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... Package Parameters for the MPC8347EA TBGA The package parameters are provided in the following list. The package type × 35 mm, 672 tape ball grid array (TBGA). Package outline Interconnects MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 54. Note that although the specifications t NEIXKH t ...

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... Package and Pin Listings Pitch Module height (typical) Solder balls Ball diameter (typical) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev 1. Sn/36 Pb/2 Ag (ZU package) 96.5 Sn/3.5Ag (VV package) 0.64 mm Freescale Semiconductor ...

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... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347EA TBGA MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package and Pin Listings 55 ...

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... Interconnects Pitch Module height (maximum) Module height (typical) Module height (minimum) Solder balls Ball diameter (typical) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev × 620 1.00 mm 2.46 mm 2. Sn/36 Pb/2 Ag (ZQ package) 96.5 Sn/3.5Ag (VR package) 0.60 mm Freescale Semiconductor ...

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... Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 40. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347EA PBGA MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package and Pin Listings 57 ...

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... AL1, AM5, AP5, AM2, AN1, AP4, AN5, AJ7, AN7, AM8, AJ9, AP6, AL7, AL9, AN8 Power Pin Type Notes Supply — DD I/O OV — DD I/O OV — DD I/O OV — — I/O OV — — — DD I/O OV — — — — — DD I/O GV — DD Freescale Semiconductor ...

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... LDP[1]/CKSTOP_IN LDP[2]/LCS[4] LDP[3]/LCS[5] LA[27:31] LCS[0:3] LWE[0:3]/LSDDQM[0:3]/LBS[0:3] LBCTL MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number W4, W3, Y3, AA6 Y1, Y6 B1, F1, K1, R4, AD4, AJ1, AP3, AP7, Y4 B2, F5, J1, P2, AC1, AJ2, AN4, AL8, ...

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... I/O OV — I/O OV — — — — — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD Freescale Semiconductor ...

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... MPH0_D5_DM/DR_D13_SESS_END MPH0_D6_SER_RCV/DR_D14 MPH0_D7_DRVVBUS/DR_D15_IDPULLUP MPH0_NXT/DR_RX_ACTIVE_ID MPH0_DIR_DPPULLUP/DR_RESET MPH0_STP_SUSPEND/DR_TX_READY MPH0_PWRFAULT/DR_RX_VALIDH MPH0_PCTL0/DR_LINE_STATE0 MPH0_PCTL1/DR_LINE_STATE1 MPH0_CLK/DR_RX_VALID MCP_OUT IRQ0/MCP_IN/GPIO2[12] IRQ[1:5]/GPIO2[13:17] MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number A27 B27 C27 D26 E26 D27 A28 F26 E27 A29 D28 B29 USB Port 0 ...

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... I LV — DD1 I OV — DD I/O OV — DD1 O LV — DD1 I/O OV — DD I/O OV — DD I/O LV — DD2 O LV — DD2 I LV — DD2 I/O LV — DD2 I/O OV — DD I/O LV — DD2 I/O OV — DD I/O OV — — — — DD Freescale Semiconductor ...

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... PCI_CLK_OUT[3]/LCS[6] PCI_CLK_OUT[4]/LCS[7] PCI_SYNC_IN/PCI_CLOCK PCI_SYNC_OUT RTC/PIT_CLOCK CLKIN TCK TDI TDO TMS TRST MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number Pin Type B5, A5, F8, B6 F14 C5 E14 DUART AK27, AN29 AL28, AM29 AP30 AN30 AP31, AM30 ...

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... Power for AV 2 — DD system PLL (1.2 V) nominal, 1.3 V for 667 MHz) Power for DDR — — DLL (1.2 V) nominal, 1.3 V for 667 MHz) Power for LBIU AV 4 — DD DLL (1.2 V) nominal, 1.3 V for 667 MHz) — — — Freescale Semiconductor ...

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... MVREF1 MVREF2 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number A2, E2, G5, G6, J5, K4, K5, L4, N4, P5, R6, T6, U5, V1, W5, Y5, AA4, AB3, AC4, AD5, AF3, AG5, AH2, AH5, AH6, AJ6, AK6, AK8, AK9, AL6 C9, D11 C6, D9 E19, E29, F7, F9, F11,F13, F15, F17, ...

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... C14, A12, D12, B11, C11, E12, A10, C10, A9, E11, E10, B9, B8, D9, A8, C9, D8, C8 A17, A14, A11, B10 D13 B14 Power Pin Type Notes Supply — — — Power Pin Type Notes Supply — DD I/O OV — DD I/O OV — DD I/O OV — Freescale Semiconductor ...

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... PCI1_GNT2/CPCI1_HS_ENUM PCI1_GNT[3:4] M66EN MDQ[0:63] MECC[0:4]/MSRCID[0:4] MECC[5]/MDVAL MECC[6:7] MDM[0:8] MDQS[0:8] MBA[0:1] MA[0:14] MWE MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number A13 E13 C13 B13 C17 C12 B12 A21 C19 C18, A19, E20 B20 ...

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... O GV — — — — — DD I/O — 9 I/O — 9 I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — — — — — DD I/O OV — DD I/O OV — — DD I/O OV — I/O OV — — — — — DD Freescale Semiconductor ...

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... MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM MPH1_D6_SER_RCV/DR_D6_SER_RCV MPH1_D7_DRVVBUS/DR_D7_DRVVBUS MPH1_NXT/DR_SESS_VLD_NXT MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ DR_STP_SUSPEND MPH1_PWRFAULT/ DR_RX_ERROR_PWRFAULT MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number General Purpose I/O Timers D27 E26 D28 G25 J24 F26 E27 E28 H25 F27 K24 ...

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... I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD I/O OV — DD I/O OV — — DD I/O OV — DD I/O OV — — I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD1 I DD1 I LV — DD1 I/O OV — DD I/O LV — DD1 DD1 Freescale Semiconductor ...

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... TSEC2_TX_EN/GPIO1[12] TSEC2_TX_CLK/GPIO1[30] UART_SOUT[1:2]/MSRCID[0:1]/LSRCID[0:1] UART_SIN[1:2]/MSRCID[2:3]/LSRCID[2:3] UART_CTS[1]/MSRCID4/LSRCID4 UART_CTS[2]/MDVAL/LDVAL UART_RTS[1:2] MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number Pin Type U26 U24 L28 M27, M28, N26, N27 W26, W24, Y28, Y27 N25 ...

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... Clocks Y1, W3 JTAG H27 H28 M24 J27 K26 Test F28 T3 PMC K27 System Control K28 M25 L27 Power Notes Supply I/O OV — DD I/O OV — DD I/O OV — — — — — — — — — — — Freescale Semiconductor ...

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... GND GV DD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number Thermal Management B15 Power and Ground Signals C15 U1 AF9 U2 A2, B1, B2, D10, D18, E6, E14, E22, F9, F12, F15, F18, F21, F24, G5, H6, J23, L4, L6, L12, L13, L14, L15, L16, ...

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... Ethernet management interface I/O (2.5 V, 3.3 V) Power for LV 2 — DD three-speed Ethernet #2 I/O (2.5 V, 3.3 V) Power for core V — DD (1.2 V) PCI, 10/100 OV — DD Ethernet, and other standard (3 DDR — reference voltage I DDR — reference voltage — — — Freescale Semiconductor ...

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... PCI agent devices in the system, to allow the MPC8347EA to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor e300 Core core_clk Core PLL ...

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... Table 57. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk Section 22.1, “Part Numbers Fully Options Freescale Semiconductor ...

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... Security core and USB modules does not exceed the respective values listed in this table. 2 The DDR data rate is 2× the DDR memory bus frequency. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor for part ordering details and contact your Freescale Sales Representative Table 58. Operating Frequencies for TBGA 400 MHz 266– ...

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... LBIUCM, DDRCM, and SPMF parameters in the reset Table 60 shows the multiplication factor Freescale Semiconductor Table 61 ...

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... CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Input Clock Frequency (MHz) csb_clk : 16 ...

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... Freescale Semiconductor 2 66.67 133 200 266 333 266 ...

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... Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency the range of 800–1800 MHz. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 63. e300 Core PLL Configuration core_clk : csb_clk Ratio 6 ...

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... Freescale Semiconductor Core Freq (MHz) 300 350 400 400 400 400 450 450 466 466 500 533 583 600 600 667 667 400 400 400 ...

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... Junction-to-ambient (at 200 ft/min) on single-layer board (1s) Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p) Junction-to-ambient (at 2 m/s) on single-layer board (1s) Junction-to-ambient (at 2 m/s) on four-layer board (2s2p) Junction-to-board thermal Junction-to-case thermal MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 533 MHz Device Input CSB Core CSB Clock ...

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... MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Symbol × where P is the power dissipation of the I/O drivers I/O I/O Value Unit Notes ψ °C Symbol Value Unit Notes °C θJA °C θJMA °C θJMA °C θJMA °C θJB °C θJC ψ °C Freescale Semiconductor ...

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... When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor , can be obtained from the equation: J × P ...

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... MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Ψ determine the junction temperature and a measure of the JT Ψ × θ θ For instance, the user can change the size of the heat θ CA Freescale Semiconductor ...

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... MEI, 75 × 85 × adjacent board, extrusion MEI, 75 × 85 × adjacent board, extrusion MEI, 75 × 85 × adjacent board, extrusion MEI, 75 × 85 × 12 mm, adjacent board side bypass MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 35 × TBGA Air Flow Thermal Resistance Natural convection 1 m/s 6 ...

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... Interface material vendors include the following: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev 603-224-9988 408-567-8082 818-842-7277 408-436-8770 800-522-2800 603-635-5102 781-935-4850 800-248-2481 Freescale Semiconductor ...

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... where junction temperature (° case temperature of the package (° junction-to-case thermal resistance (°C/W) θ power dissipation (W) D MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor × θ 888-642-7674 800-347-4572 Thermal 89 ...

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... V Figure 42, one to each of the four AV 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 42. PLL Power Supply Filter Circuit respectively). The through a DD pins (or L2AV ) DD DD Freescale Semiconductor DD DD ...

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... GND. Then the value of each resistor is varied until the pad voltage is OV output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and R MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor required. Unused active high inputs should be ...

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... PCI Output Clocks (Not Including PCI (Including Output Clocks) PCI_SYNC_OUT) 25 Target 42 Target 25 Target 42 Target NA Table 105°C. j and R are designed to be close to each SW2 SW1 . The measured voltage is term × (V ÷ source term 1 DDR DRAM Symbol 20 Target Target DIFF Freescale Semiconductor – 1 Unit ...

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... Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor NOTE Ordering Information ...

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... Free PBGA for more information on available package types. Table 71. SVR Settings Package TBGA TBGA PBGA PBGA Processor Platform Revision 3 Frequency Frequency Level e300 core D = 266 B = 3.1 4 speed F = 333 AD = 266 AG = 400 AJ = 533 AL = 667 SVR (Rev. 3.0) 8052_0030 8053_0030 8054_0030 8055_0030 Freescale Semiconductor ...

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... Section 18.3, “Package Parameters for the MPC8347EA and PBGA from 95.5 Sn/0.5 Cu 96.5 Sn/3.5 Ag. • In Table • In Table • In Table and DDR2. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Figure 44. MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ TBGA/ PBGA ...

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... Frequencies for TBGA,” Requirements,“ deleted last two paragraphs and after first (output data is driven on falling edge of clock Figure 21, Figure 23, and 56. added column for 400 MHz. row to show nominal core supply DD for 333 MHz ddkhds Freescale Semiconductor Figure 24 CISKEW ...

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... Listing,” in row AVDD3 changed power supply from “AVDD3” to ‘—.’ 0 3/2006 Initial public release. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Substantive Change(s) + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0. 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8. ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...