MC68020FE33E Freescale Semiconductor, MC68020FE33E Datasheet - Page 12

no-image

MC68020FE33E

Manufacturer Part Number
MC68020FE33E
Description
IC MICROPROCESSOR 32BIT 132CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68020FE33E

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68020FE33E
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68020FE33E1E30G
Manufacturer:
MOT
Quantity:
5 510
9/29/95
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
7-31
7-32
7-33
7-34
7-35
7-36
7-37
7-38
7-39
7-40
7-41
7-42
7-43
7-44
xvi
Number
Figure
Coprocessor Address Map in MC68020/EC020 CPU Space .......................... 7-7
Coprocessor Interface Register Set Map ......................................................... 7-7
Coprocessor General Instruction Format (cpGEN) .......................................... 7-8
Coprocessor Interface Protocol for General Category Instructions.................. 7-10
Coprocessor Interface Protocol for Conditional Category Instructions ............ 7-11
Branch on Coprocessor Condition Instruction Format (cpBcc.W) ................... 7-12
Branch on Coprocessor Condition Instruction Format (cpBcc.L) ..................... 7-12
Set on Coprocessor Condition Instruction Format (cpScc) .............................. 7-13
Test Coprocessor Condition, Decrement, and Branch
Trap on Coprocessor Condition Instruction Format (cpTRAPcc) ..................... 7-15
Coprocessor State Frame Format in Memory .................................................. 7-17
Coprocessor Context Save Instruction Format (cpSAVE) ............................... 7-20
Coprocessor Context Save Instruction Protocol .............................................. 7-21
Coprocessor Context Restore Instruction Format (cpRESTORE) ................... 7-22
Coprocessor Context Restore Instruction Protocol .......................................... 7-23
Control CIR Format .......................................................................................... 7-25
Condition CIR Format ...................................................................................... 7-26
Operand Alignment for Operand CIR Accesses .............................................. 7-26
Coprocessor Response Primitive Format ........................................................ 7-28
Busy Primitive Format ...................................................................................... 7-30
Null Primitive Format........................................................................................ 7-31
Supervisor Check Primitive Format.................................................................. 7-33
Transfer Operation Word Primitive Format ...................................................... 7-33
Transfer from Instruction Stream Primitive Format .......................................... 7-34
Evaluate and Transfer Effective Address Primitive Format.............................. 7-35
Evaluate Effective Address and Transfer Data Primitive Format ..................... 7-35
Write to Previously Evaluated Effective Address Primitive Format .................. 7-37
Take Address and Transfer Data Primitive Format .......................................... 7-39
Transfer to/from Top of Stack Primitive Format ............................................... 7-40
Transfer Single Main Processor Register Primitive Format ............................. 7-40
Transfer Main Processor Control Register Primitive Format ........................... 7-41
Transfer Multiple Main Processor Registers Primitive Format ......................... 7-42
Register Select Mask Format ........................................................................... 7-42
Transfer Multiple Coprocessor Registers Primitive Format.............................. 7-43
Operand Format in Memory for Transfer to –(An) ........................................... 7-44
Transfer Status Register and ScanPC Primitive Format.................................. 7-44
Take Preinstruction Exception Primitive Format .............................................. 7-45
MC68020/EC020 Preinstruction Stack Frame ................................................. 7-46
Take Midinstruction Exception Primitive Format .............................................. 7-47
MC68020/EC020 Midinstruction Stack Frame ................................................. 7-47
Take Postinstruction Exception Primitive Format............................................. 7-48
Instruction Format (cpDBcc)........................................................................... 7-14
LIST OF ILLUSTRATIONS (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
SECTION 1: OVERVIEW
M68020 USER’S MANUAL
Go to: www.freescale.com
Title
UM Rev.1.0
MOTOROLA
Number
Page

Related parts for MC68020FE33E