MC68020FE33E Freescale Semiconductor, MC68020FE33E Datasheet - Page 174

• Manufacturer Part Number: MC68020FE33E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

main processor reads an invalid format word from the save CIR, it writes the abort mask to
the control CIR and initiates format error exception processing (refer to 7.5.1.5 Format
Errors).
7.2.3.2.4 Valid Format Word. When the main processor reads a valid format word from
the save CIR during the cpSAVE instruction, it uses the length field to determine the size
of the coprocessor state frame to save. The length field in the lower eight bits of a format
word is relevant only in a valid format word. During the cpRESTORE instruction, the main
processor uses the length field in the format word read from the effective address in the
instruction to determine the size of the coprocessor state frame to restore.
The length field of a valid format word, representing the size of the coprocessor state
frame, must contain a multiple of four. If the main processor detects a value that is not a
multiple of four in a length field during the execution of a cpSAVE or cpRESTORE
instruction, the main processor writes the abort mask (refer to 7.2.3.2.3 Invalid Format
Word) to the control CIR and initiates format error exception processing.
7.2.3.3 COPROCESSOR CONTEXT SAVE INSTRUCTION. The M68000 coprocessor
context save instruction category consists of one instruction. The coprocessor context
save instruction, denoted by the cpSAVE mnemonic, saves the context of a coprocessor
dynamically without relation to the execution of coprocessor instructions in the general or
conditional instruction categories. During the execution of a cpSAVE instruction, the
coprocessor communicates status information to the main processor by using the
coprocessor format codes.
7.2.3.3.1 Format. Figure 7-15 shows the format of the cpSAVE instruction. The first word
of the instruction, the F-line operation word, contains the CpID code in bits 11–9 and an
M68000 effective address code in bits 5–0. The effective address encoded in the cpSAVE
instruction is the address at which the state frame associated with the current context of
the coprocessor is saved in memory.
The control alterable and predecrement addressing modes are valid for the cpSAVE
instruction. Other addressing modes cause the MC68020/EC020 to initiate F-line emulator
exception processing as described in 7.5.2.2 F-Line Emulator Exceptions.
The instruction can include as many as five effective address extension words following
the F-line operation word. These words contain any additional information required to
calculate the effective address specified by bits 5–0 of the F-line operation word.
MOTOROLA
Figure 7-15. Coprocessor Context Save Instruction Format (cpSAVE)
15
1
14
1
13
1
12
Freescale Semiconductor, Inc.
1
For More Information On This Product,
11
EFFECTIVE ADDRESS EXTENSION WORDS (0–5 WORDS)
CpID
Go to: www.freescale.com
M68020 USER’S MANUAL
9
1
8
0
7
6
0
5
EFFECTIVE ADDRESS
0
7- 21